Low power line system and method

Details Low power line system and method Low power line system and method

1998-03-27

1999-11-02

Nelms, David

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

36523006, 365188, G11C 1604

Patent

active

059782820

ABSTRACT:
The low power data line and method may comprise a line (30, 102) connecting a plurality of devices (60, 104) to an output (32, 104). The devices (60, 104) may be independently accessed to provide data to the output (32) along the line (30, 102). A switch (40, 120) may be disposed in the line (30, 102) to selectively disconnect a segment (52, 132) of the line (30, 102) connected to at least one of the devices (60, 104) from the output (32).

REFERENCES:
patent: 535427 (1895-10-01), Fujishima et al.
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5721862 (1998-02-01), Sartore et al.
patent: 5808959 (1998-09-01), Kengeri et al.

Affiliated with

Also associated with

Rating

Low power line system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power line system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power line system and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2144774