Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1998-07-08
2001-04-03
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S082000, C326S080000, C323S290000, C327S111000
Reexamination Certificate
active
06211701
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to drive circuitry and more specifically to a low power switching circuit that can also reduce ground bouncing.
BACKGROUND OF THE INVENTION
Advances in the fields of computing, communications and consumer electronics have created conflicting requirements for electronic devices. On one hand, significantly increased data bandwidth is necessary for applications such as three-dimensional (3-D) computer graphics, high-definition moving pictures and high quality voice and information communications. On the other hand, the emergence of portable computers, telephones and other electronic devices and so-called green standards for personal computers has driven the need for reduced power consumption.
High bandwidth data processing is accomplished through use of multiple parallel data lines at increasingly higher frequencies. Power consumption and ground bounce, however, increase with the number of switching lines and also increase with augmentations in the operating frequency of the lines. Hence, a need exists to provide interface circuits for providing a high data bandwidth while reducing ground bounce and minimizing the power dissipated by the signal lines.
Several arrangements have been proposed for lowering the power dissipated when driving a high number of parallel lines. For example, Yamauchi et al., “An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's”, IEEE Journal of Solid-State Circuits, Vol.30, No. 4, April 1995, p.423, explain how energy dissipation can be lowered by reducing the voltage swing of the data lines. The swing of the lines is reduced by a given factor to achieve this. In an article by Hiraki et al. “Data-Dependent Logic Swing Internal Bus Architecture for Ultra low-Power LSI's”, IEEE Journal of Solid-State Circuits Vol. 30, No. 4, April 1995, p.397, the reduction in the logic swing depends on the data passed through the bus.
Both systems use reduction of the voltage swing to obtain lower power dissipation when driving lines. The drawbacks of these systems are two-fold. First, bit-error rate (BER) increases at the receiving side due to reduced noise margins. Also, these systems are not fully compatible with existing data buses. Moreover, at the receiver side(s) the circuitry needs to be adapted to the specific proposed signaling methods. Neither of these papers teaches a backward compatible, voltage-independent and data pattern independent method for reducing data bus power consumption.
Additionally, in high-speed circuits the conventional capacitive model of a data line must be replaced by a transmission line model. Consequently, data transmission via conventional driver interfaces is impossible because of the large signal distortion due to reflections inherent in the open transmission line scheme. Hence a need exists to provide interface circuitry compatible with both capacitive and transmission lines.
Another problem associated with prior art devices is ground bounce caused by simultaneous switching of multiple lines. This noise in power lines originates from the fast transient current in the package and printed circuit board (PCB) parasitic inductances. Ground bounce also causes under- and overshoots outside the allowed voltage swings of the lines. On many integrated circuits, a large number of input/output (I/O) pins are used for power and ground leads. This ensures a low inductance path to the power supply lines and hence reduces ground bounce.
Several arrangements have been proposed for lowering the ground bounce in order to reduce the number of power and ground I/O pins. For example, papers have been published by C. S. Choy et al., “A Low Power-Noise Output Driver with an Adaptive Characteristic Applicable to a Wide Range of Loading Conditions,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, June 1997, p.913 and Thaddeus J. Gabara et al., “Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers, IEEE Journal of Solid-State Circuits, Vol. 32, No. 3, March 1997, p.407). None of these alternatives, however, reduces power switching dissipation of switching lines. In fact, several even increase power consumption.
SUMMARY OF THE INVENTION
In one aspect, the present invention is directed toward a novel apparatus and method for changing the voltage level on a line with reduced power dissipation. The energy is reduced without significantly lowering the voltage swing and/or sacrificing noise margins. Alternatively, the invention can also be used in combination with a reduced voltage swing to achieve even lower power dissipation.
In another aspect, the present invention is directed toward a novel apparatus and method for switching a line with reduced ground bounce.
In one embodiment, a drive circuit comprises an output terminal for connection to a signal line. An inductor is coupled between the signal line and a reference voltage node. A switch is coupled between the signal line and the reference voltage node. When the switch is closed, the inductor is coupled between the reference voltage node and the signal line. When the switch is open, the inductor is not coupled between the reference voltage node and the signal line.
In another embodiment, a method of switching a line from a first voltage level to a second voltage level is disclosed. A signal line is inductively coupled to a reference voltage. The reference voltage being held at a level between the first and second voltage levels. The line is then decoupled from the reference voltage when the line substantially reaches a maximum bias relative to the reference voltage. After decoupling the line, the line is forced to the second voltage level. In one aspect, capacitive energy stored with a first charging direction on the signal line is converted into magnetic energy or magnetic energy is converted into capacitive energy on the signal line.
In yet another embodiment, a switching circuit includes a first switch with a current path coupled between a virtual ground node and an output node. The circuit also includes a second switch with a current path coupled between a HIGH voltage node and the output node and a third switch with a current path coupled between a LOW voltage node and the output node. In response to the receipt of an input signal, a control circuit enables the first switch for a selected period of time and, after the selected period of time, disables the first switch and enables only one of the second and third switches.
The present invention has a number of advantages over prior art switching circuits. For example, power dissipation and ground bounce can be reduced. The preferred embodiment of the invention also allows for a system that snaps the voltage of the lines to one of the allowed voltage levels and provides low output impedance. The values of the allowed voltage levels car be pre-defined. For example, in the preferred embodiment, these voltage levels are standard voltages such as 0 volts and 3.3 volts or 5 volts. Use of standard voltages makes the devices backwards compatible.
The preferred embodiment also permits for a means to estimate the end-of-conversion moment during the state changes.
Additionally, the preferred embodiments of the invention may also be used to switch transmission lines.
The above and further advantages and features of the invention will be more fully apparent from the following detailed description with accompanying drawings.
REFERENCES:
patent: 4291240 (1981-09-01), Rosler
patent: 4370570 (1983-01-01), Dash et al.
patent: 4613771 (1986-09-01), Gal
patent: 5744943 (1998-04-01), Tokai
patent: 5754011 (1998-05-01), Trus et al.
patent: 5883505 (1999-03-01), Magazzu et al.
patent: 5929620 (1999-07-01), Dobkin et al.
patent: 0 395 146 A1 (1990-10-01), None
patent: 0 680 148 A2 (1995-11-01), None
patent: 62029312 (1987-02-01), None
patent: WO 97/09783 (1997-03-01), None
IEEE Journal of Solid State Circuits, “A 500-Megabyte/s Data-Rate 4.5M DRAM,” vol. 28, No. 4, Apr. 1993, pp. 490-498.
IEEE Journal of Solid State Cir
Devisch Frédérick
Kuijk Maarten
Stiens Johan
Vounckx Roger Andre
Chang Daniel D.
Rose Research, LLC
Slater & Matsil LLP
Tokar Michael
LandOfFree
Low power line switching circuit, device and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low power line switching circuit, device and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power line switching circuit, device and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2537241