Low power interface circuit

Details Low power interface circuit Low power interface circuit

1993-04-20

1995-01-03

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Logic level shifting

326121, 327530, H03K 19094

Patent

active

053789431

ABSTRACT:
The interface circuit of the present invention adjusts the signal voltage across a leaking transistor such that the leakage is reduced while also shunting out the adjustment means when the adjustment means impedes the operation of the interface circuit. One embodiment of the present invention is a level translator comprised of a level shifting stage coupled to a buffer stage. The level shifting stage has its power source coupled to a current shunting device. The current shunting device is connected in parallel across the first P-channel device of the level shifting stage. The first P-channel device of the level shifting stage is connected in series with a second P-channel device having its drain connected to a drain of a first N-channel device wherein the first N-channel device has its source connected to a drain of a second N-channel device. The current shunting device is formed from a single P-channel device. The connection between the drains of the second P-channel and the first N-channel device of the level shifting stage is an input to an inverter, which in turn, has its output connected to the input of the current shunting device. When the input to the level shift stage is at the high voltage logic signal level, the input to the inverter is low and the output of the inverter is at a high voltage logic signal level. The high voltage logic signal level then turns off the P-channel device of the current shunting device. The first P-channel device of the level shifting stage has its gate connected to its drain which reduces leakage current in the level shifting stage and reduces the power consumed by the interface circuit when the current shunting device is turned off. When the input to the level shift stage is at the low voltage logic signal level, the input to the inverter is high and the output of the inverter is at a low voltage logic signal level. The low voltage logic signal level allows the current shunting device to directly supply current to the second P-channel device of the level shifting stage and shunts out the first P-channel device. Therefore, the shunted out device does not interfere with the performance of the level shift stage of the interface circuit.

REFERENCES:
patent: 4786830 (1988-11-01), Foss
patent: 4825106 (1989-04-01), Tipon et al.
patent: 4857763 (1989-08-01), Sakurai et al.
patent: 4859870 (1989-08-01), Wong et al.
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patent: 5087841 (1992-02-01), Rogers
patent: 5151620 (1992-09-01), Lin
patent: 5160855 (1992-11-01), Dobberpuhl
patent: 5223751 (1993-06-01), Simmons et al.

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