Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-09-20
2002-05-21
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06393510
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a receiver, and in particular to a low power high-speed bus receiver which can receive a pair of differential signals from a single bus or sequentially receive plural pairs of differential signals from plural buses to obtain the corresponding logic value or values.
2. Description of the Invention
In a semiconductor circuit, such as a DRAM, a bus receiver that receives a bus signal from a single bus is usually constructed with an inverter or a buffer. For this bus receiver, as long as the bus signal has a voltage higher or lower than predetermined voltage levels, the bus receiver will generate a logic high or a logic low. Further, the bus receiver not only recovers the bus signal, but also impedance matches with the next-stage circuit, preventing unnecessary distortions as a result of small input impedance.
However, the bus receiver constructed with an inverter or a buffer has a longer delay time and a larger signal swing. Accordingly, analog circuits, such as comparator circuits, are used to develop an analog bus receiver. The analog bus receiver has a shorter delay time. However, the analog bus receiver also needs a bias voltage (usually the average of the highest voltage level and the lowest voltage level), consumes DC current, and has a low noise immunity.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a low power high-speed bus receiver for receiving a pair of differential signals or sequentially receiving plural pairs of differential signals that employs a differential amplifier to make the delay time shorter than that of the conventional bus receiver which employs an inverter or a buffer.
It is another object of the present invention to provide a low power high-speed bus receiver which employs input switches to control the receiving of a pair of differential signals or plural pairs of differential signals and to prevent bus conflicts.
It is another object of the present invention to provide a low power high-speed bus receiver which employs power switches to control the input of external power supplies and to prevent power losses.
It is another object of the present invention to provide a low power high-speed bus receiver which employs a differential amplifier to amplify the difference between a pair of differential signals respectively input to a positive input terminal and a negative input terminal of the differential amplifier, so that it is not necessary to provide a bias voltage and the noise immunity is also increased.
To achieve the above and other objects, the present invention provides a low power high-speed bus receiver which receives a pair of differential signals to obtain the corresponding logic value. The bus receiver includes a differential amplifier, a pair of input switches and a pair of power switches. The differential amplifier has a pair of input terminals and a pair of power terminals. The pair of input switches are respectively connected between the pair of input terminals of the differential amplifier and the pair of differential signals. The pair of input switches are turned on for a predetermined time period to transmit the pair of differential signals to the differential amplifier. The pair of power switches are respectively connected between the pair of power terminals of the differential amplifier and a pair of external power supplies. The pair of power switches are turned on after the pair of input switches are turned on for the predetermined time period to enable the differential amplifier to amplify the difference between the pair of differential signals to obtain the corresponding logic value.
The present invention also provides a low power high-speed bus receiver for sequentially receiving several pairs of differential signals from several buses. The bus receiver includes a differential amplifier, several pair of input switches and a pair of power switches. The differential amplifier has a pair of input terminals and a pair of power terminals. The plural pairs of input switches are respectively connected between the pair of input terminals of the differential amplifier and the plural pairs of differential signals. The plural pairs of input switches are sequentially turned on for a predetermined time period to transmit each of the plural pairs of differential signals to the differential amplifier. The pair of power switches are respectively connected between the pair of power terminals of the differential amplifier and a pair of external power supplies. The pair of power switches are turned on after each of the plural pairs of input switches are turned on for the predetermined time period to enable the differential amplifier to amplify the difference between each of the pairs of differential signals to obtain the corresponding logic values.
In the above mentioned bus receivers, the pair (or the plural pairs) of input switches can be a pair (or plural pairs) of transmission gates, and the pair of power switches can be a pair of transistors.
REFERENCES:
patent: 3906248 (1975-09-01), Vieira et al.
patent: 3906372 (1975-09-01), Schatter et al.
patent: 4535257 (1985-08-01), Hareyama
patent: 5059829 (1991-10-01), Flannagan et al.
patent: 5329187 (1994-07-01), Crispie et al.
patent: 5721594 (1998-02-01), Gurley et al.
Intellectual Property Solutions, P.L.L.C.
Thai Xuan M.
Vanguard International Semiconductor Corporation
LandOfFree
Low power high-speed bus receiver does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low power high-speed bus receiver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power high-speed bus receiver will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2828751