Low power flip-flop circuit

Details Low power flip-flop circuit Low power flip-flop circuit

2003-09-26

2004-12-07

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000, C327S212000

Reexamination Certificate

active

06828837

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flip-flop circuit and, more particularly, to a flip-flop circuit with lower power consumption.
A claim of priority under 35 U.S.C. 119 is made to Korean Patent Application No. 2002-64666 filed on Oct. 22, 2002, the entire contents of which are hereby incorporated by reference.
2. Description of the Related Art
A conventional flip-flop circuit, as shown in
FIG. 1
, is generally configured to include a clock buffer
110
, a master latch gate
120
, a master latch
130
, a slave latch gate
140
, and a slave latch
150
. When an internal clock signal CK is a low level, the master latch gate
120
turns on to transfer an input signal D to the master latch
130
and the slave latch gate
140
turns off. To the contrary, when the internal clock signal CK shifts from a low level to a high level, the master latch gate
120
turns off and the input signal D is not transferred to the master latch
130
. When the clock signal CK is high level, the slave latch gate
140
turns on and thereby the input signal D, which has been stored in the master latch
130
when the internal clock signal CK is a low level, is transferred to the slave latch
150
that provides an output signal Q through an inverter INV
2
therefrom.
In the flip-flop described above, there is no power consumption due to switching during null signal states in the master latch
130
and the slave latch
150
when the input signal does not vary (i.e., the input signal is equal to the output signal). However, even when the input signal does not vary, the clock buffer which receives the external clock signal and generates the internal clock signal from the external clock signal operates. Accordingly, power consumption due to switching in the clock buffer occurs.
Recently, various efforts have been made to reduce power consumption due to switching operations in a clock buffer.
FIG. 2
illustrates a conventional flip-flop circuit that reduces the power consumption in the clock buffer. The flip-flop circuit of
FIG. 2
has a comparing circuit
220
for comparing the input signal D with the output signal Q, a pulse generating circuit
240
for generating an internal clock signal with a small pulse width in synchronization with the external clock signal, and a control circuit
230
for controlling the output signal PGO of the pulse generating circuit
240
using the comparison result from the comparing circuit
220
. When the input signal D does not vary, the power consumption of the flip-flop circuit can be reduced by blocking the path from the pulse generating circuit
240
through the control circuit
230
to the clock buffer
210
. However, the flip-flop circuit shown in
FIG. 2
includes pulse generating circuit
240
, in addition to the circuit part for generating the output signal by synchronizing the input signal with the clock signal. This pulse generating circuit
240
has high power consumption.
FIG. 3
illustrates another conventional type of flip-flop circuit capable of reducing power consumption at the clock buffer, which is disclosed in U.S. Pat. No. 6,204,707. The flip-flop circuit illustrated in
FIG. 3
is provided with a comparing circuit
330
, an internal clock generating circuit
340
, and a latch
320
. The flip-flop circuit generates an internal clock signal with a small pulse width in synchronization with the external clock signal CLK, only when the input signal D does not vary. As the flip-flop circuit shown in
FIG. 3
does not employ any additional pulse generating circuit, the power consumption thereof is lower than that of the flip-flop circuit shown in FIG.
2
. The internal clock generating circuit
340
compares the compared result of the input signal D and the output signal Q, with the external clock signal CLK, to generate an internal clock signal.
However, the internal clock generating circuit
340
is not wholly controlled by way of the comparative difference between the input signal D and the output signal Q. That is, the voltage level of the output terminal of an AND gate
344
is dependent on the external clock signal CLK, and hence, power consumption is caused by operation of the AND gate
344
. Furthermore, the start of the internal clock signal (the rising edge of its waveform) at the flip-flop circuit shown in
FIG. 3
is synchronized with the external clock signal, and the termination of the internal clock signal (the falling edge of its waveform) is synchronized with the output of the comparing circuit
330
. Therefore, with the flip-flop circuit shown in
FIG. 3
, the pulse width of the internal clock signal is variable in accordance with the operation state of the comparing circuit
330
.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a flip-flop circuit having reduced power consumption.
To achieve this and other objects, the flip-flop circuit of an embodiment of the invention is provided such that when a variation does not appear at an input signal, an output buffer and an internal clock generating circuit are made not active, thereby reducing power consumption.
According to one aspect of the present invention, the flip-flop circuit includes a latch that receives and holds an input signal under the control of an internal clock signal, a comparing circuit that compares the input signal with the output signal of the latch to provide a compared result, and an internal clock generating circuit that receives an external clock signal and generates an internal clock signal under the control of the output signal of the comparing circuit. The internal clock generating circuit controls an entrance path and passing of the external clock signal using the output signal of the comparing circuit, delays the external clock signal for a predetermined time and inverts the delayed external clock signal. The internal clock generating circuit generates an internal clock signal with a pulse width smaller than the pulse width of the external clock signal by means of a NAND operation performed on the external clock signal and the inverted delayed external clock signal. The internal clock signal is established with rising and falling edges all synchronized with the external clock signal.
The internal clock generating circuit includes an inverter that inverts the output signal of the comparing circuit from a first node and transmits the inverted signal to a second node, and a transmission gate with a first input terminal connected to the first node and a second input terminal connected to the second node that receives the external clock signal and transmits the received signal to a third node. The internal clock generating circuit further includes a PMOS transistor having a source terminal connected to a supply voltage, a gate terminal connected to the second node, and a drain terminal connected to the third node. A delay circuit receives a signal from the third node, and delays the external clock signal for the predetermined time and inverts the delayed external clock signal. A NAND circuit receives the delayed inverted external clock signal, and performs the NAND operation on the external clock signal and the delayed inverted external clock signal.
In an aspect of the embodiment, the delay circuit is formed of odd-numbered inverters. Also, in the internal clock generating circuit, the PMOS transistor maintains the third node at a high level when the transmission gate turns off.


REFERENCES:
patent: 5859546 (1999-01-01), Yamauchi
patent: 6204707 (2001-03-01), Hamada et al.
patent: 6630853 (2003-10-01), Hamada
patent: 4-298115 (1992-10-01), None

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