Low power eprom logic cell and logic arrays thereof

Details Low power eprom logic cell and logic arrays thereof Low power eprom logic cell and logic arrays thereof

1987-08-06

1989-02-07

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365189, G11C 1134, G11C 700

Patent

active

048036617

ABSTRACT:
A plurality of logic cells that may be iteratively connected in the form of an array to form an electrically programmable logic device. Each such cell utilizes a plurality of threshold modifiable CMOS transistors as permanent memory storage devices to provide sixteen possible Boolean logic functions for two input variables. The logical operation of the circuit is controlled by simply changing the programming threshold of the memory transistors. These transistors are buffered by drivers and are provided with a switched load transistor. This substantially reduces memory transistor size and power consumption and permits long term program voltage retention. An 18.times.9 cell array embodiment is illustrated along with programming and cell selection logic. A 9.times.9 cell array embodiment is also shown.

REFERENCES:
patent: 4527257 (1985-07-01), Cricchi
patent: 4611308 (1986-09-01), Lonky

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