Low power dynamic logic circuit

Details Low power dynamic logic circuit Low power dynamic logic circuit

2001-05-11

2002-12-10

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000

Reexamination Certificate

active

06492839

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a dynamic logic circuit, and more particularly, to a low power dynamic logic circuit.
2. Description of the Related Art
CMOS dynamic circuits originated in the 1980s. Since the CMOS circuit employing repetitive transistor networks (NMOS transistor network and PMOS network) to implement the circuit required excessive hardware, a single-side transistor network (only NMOS transistor network or PMOS network) replaced the CMOS circuit. However, the single-side transistor network is not supposed to lose the advantage of no static power consumption of the CMOS circuit. With this in mind, the CMOS dynamic circuit is developed and fabricated.
FIG. 1
shows a conventional dynamic logic circuit. In
FIG. 1
, the dynamic logic circuit comprises a PMOS transistor
102
, a logic block
104
and an NMOS transistor
106
. The PMOS transistor
102
and the NMOS transistor
106
are controlled by the same clock signal &phgr;, which is illustrated in FIG.
1
B. The logic block
104
is used to implement a Boolean function. The dynamic logic circuit as shown in
FIG. 1
controlled by the clock signal &phgr; works in two phases, that is, a precharge phase and an evaluation phase. When the circuit works in the precharge phase, &phgr;=0, the PMOS transistor
102
is turned on, and the NMOS transistor
106
is turned off. Consequently, the output terminal O is charged to a high voltage (logic 1) via the PMOS transistor
102
. When the circuit works in the evaluation phase, &phgr;=1, the PMOS transistor
102
is turned off, and the NMOS transistor
106
is turned on. Meanwhile, the logic block
104
is connected to the NMOS transistor
106
in series, so that the logic of the output terminal O is determined by the input terminal i to complete the Boolean function of the circuit.
FIG. 2A
shows the way to use a domino circuit to construct the dynamic logic circuit. In
FIG. 2A
, two stages of domino circuit logic gates
202
and
204
are coupled to each other. The logic gates
202
and
204
are similar to each other with different complete logic. For example, the logic gate
202
comprises a logic unit
206
coupled to a driver unit
208
, and the logic unit
206
comprises a PMOS transistor
210
, a logic block
212
and an NMOS transistor
214
coupled together. The logic block
212
comprises an NMOS transistor
226
coupled to an NMOS transistor
228
. The logic gate
204
comprises a logic unit
216
coupled to a driver unit
218
. The logic unit
216
comprises a PMOS transistor
220
, a logic block
222
and an NMOS transistor
224
coupled together. The logic block
222
comprises an NMOS transistor
230
. The PMOS transistor
210
, the PMOS transistor
220
, the NMOS transistor
214
and the NMOS transistor
224
are controlled by the same clock signal &phgr;. The driver units
208
and
218
are made of inverters. The relative waveforms of the operation of the circuit are shown as FIG.
2
B. The domino circuit is working in two phases, the precharge phase (&phgr;=0) and the evaluation phase (&phgr;=1). When &phgr;=0, the outputs Q and R of the logic units
206
and
216
are charged up to a high voltage. Through the inverter, the outputs P and Z of the logic gates
202
and
204
are 0. After &phgr;=1, initially, as the outputs P and Z are both low voltage, so that the NMOS transistor
230
to implement the Boolean function is shut off. However, when A and B are both logic 1, the output of the logic unit
206
is 0 after a time delay. Through the inverter, the output P is raised to logic 1. Similarly, when P is logic 1, Z is raised to logic 1 after a time delay. Accordingly, the data evaluation operation is performed sequentially without causing the problem of data race.
FIG. 3A
shows a way of using a clock delay circuit to construct a dynamic logic circuit. In
FIG. 3A
, two stages of clock delay circuit logic gates
302
and
304
are coupled to each other. The logic gate
302
comprises a logic unit
306
that further comprises a PMOS transistor
308
, a logic block
310
and an NMOS transistor
312
coupled together. The PMOS transistor
308
and the NMOS transistor
312
are controlled by the clock signal &phgr;. The logic gate
304
comprises a logic unit
314
that further comprises a PMOS transistor
316
, a logic block
318
and an NMOS transistor
320
. The PMOS transistor
316
and the NMOS transistor
320
are controlled by the clock signal &phgr;
d
. The relative waveforms of the operation of the circuit are shown in FIG.
3
B. In
FIG. 3B
, the clock delay circuit is operated under two phases, that is, a precharge phase (&phgr;=0, &phgr;
d
=0) and an evaluation phase (&phgr;=1 and &phgr;
d
=1). When &phgr;=0, &phgr;
d
=0, the circuit is in the precharge phase. The outputs P and Z of the logic gates
302
and
304
are logic 1. When &phgr;=1, the logic gate
302
starts the evaluation. Meanwhile, &phgr;
d
is still 0. The output P is varied to logic 0 only when the input signals A and B are both logic 1. Consequently, &phgr;
d
is changed to 1. Meanwhile, the input of the logic gate
304
is stabilized, the output Z is not damaged by data race, and a correct evaluation can be performed.
Both the domino circuit and clock delay circuit are operated by applying the technique of an inverter gate or a clock delay to the logic unit. That is, the major part is still the logic unit. Therefore, if the performance of the logic unit is enhanced, for example, the operation speed is increased and the power consumption is reduced, the overall assembly of circuit can be enhanced.
FIG. 4
illustrates a conventional logic unit of a dynamic logic circuit with a NOR function. In
FIG. 4
, the logic unit of the logic circuit comprises a PMOS transistor
402
, a logic block
404
and an NMOS transistor
406
coupled together. The PMOS transistor
402
and the NMOS transistor
406
are controlled by a clock signal &phgr;. The logic block
404
comprises k NMOS transistors connected in parallel. That is, the logic unit implements the NOR function with k inputs. When the logic block
404
connects k NMOS transistors in parallel, the parasitic capacitance of the drain and source regions are significant. The lump capacitor of the drain regions (including the parasitic capacitor and the wiring capacitor) is denoted by C
1
408
, while the lump capacitor of the source regions (including the parasitic capacitor and the wiring capacitor) is denoted by C
2
410
. When &phgr;=0 the PMOS transistor
402
charges the capacitors C
1
408
and C
2
410
up to V
DD
and V
DD
−V
TN
, wherein V
DD
is the operation voltage, and V
TN
is the threshold voltage of the NMOS transistor. When &phgr;=0, most of the input combinations (with a probability of (2
k
−1)/2
k
) enables the charges stored in C
1
408
and C
2
410
to leak. As the speed of the logic unit is determined according to the transition from 1 to 0 of the output terminals, the discharging time will seriously affect the operation speed. In addition, this dynamic power consumption is significant with a high probability and is a major factor that affects the power consumption of the circuit.
According to the above, the conventional dynamic logic circuit still has a lot drawbacks such as:
1. Significant power consumption.
2. Long operation time.
SUMMARY OF THE INVENTION
The invention provides a novel CMOS basic dynamic logic circuit to improve the problems of large power consumption and long operation time for the conventional dynamic logic circuit.
The novel dynamic logic circuit provided by the invention comprises a charge unit, coupled to a first clock signal, and a discharge unit, coupled to a second clock signal and the charge unit. The first and the second clock signal are in inverted phase to each other.
The charge unit comprises a PMOS transistor, an NMOS transistor, a feedback PMOS transistor and a logic gate. The PMOS transistor has a gate coup

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