Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-12-19
2003-05-20
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S057000, C327S206000
Reexamination Certificate
active
06566910
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the reduction of power consumption in digital circuits that rely upon a resistive load design such as pseudo NMOS and/or pseudo PMOS.
BACKGROUND INFORMATION
Reducing power consumption in digital circuits has become increasingly important, especially for real time clocking (RTC) applications which are operated by a low capacity battery (typically 200 mA-hr). For these applications, having low power consuming circuit elements may be essential to prolong battery lifetime.
Power consumption determines how much heat the circuit dissipates and how much energy is consumed. It can be decomposed into two components: static and dynamic. The dynamic component only occurs during transients, i.e. when the circuit is switching. It is due to the charging of capacitive elements and temporary current paths between the supply rails, and is, therefore, proportional to the switching frequency and duration: the greater the number of switching events and the longer they occur, the greater the dynamic power consumption. The static component on the other hand is present even when no switching occurs and is caused by static conductive paths between the supply rails or by leakage currents.
A bistable pulse generator, known as the Schmidt Trigger, is frequently used in RTC applications to “clean up” noisy signals by switching at a different threshold on rising and falling edges of an input signal.
FIG. 1
a
is a transistor level diagram of a conventional Schmidt Trigger circuit. This type of circuit may consume a large current during switching transitions, i.e. a high dynamic power consumption. As
FIG. 1
b
illustrates, intermediate transistors MP
3
and MN
3
provide a direct current path from the power source to ground during the transition phase. As a result, the dynamic power consumption of the Schmidt Trigger may be quite significant.
FIG. 2
a
shows the voltage characteristic of Schmidt Trigger circuit
1000
during a high to low transition.
FIG. 2
b
demonstrates the current consumption of Schmidt Trigger circuit
1000
during this same period.
FIG. 2
a
shows input voltage v(in) decreasing linearly while output voltage v(out) remains constant at a high potential (~1.5 v) until input voltage v(in) reaches a particular threshold level (~0.3 v) whereupon output voltage v(out) drops suddenly and sharply (~0.0 v). Corresponding to the transition from a high to low voltage level, a significant current i(mp
3
) flows via intermediate transistor MP
3
as indicated in
FIG. 2
b.
FIG. 3
a
shows the voltage characteristic of Schmidt Trigger circuit
1000
during a low to high transition.
FIG. 3
b
demonstrates the current consumption of Schmidt Trigger circuit
1000
during this same period
FIG. 3
a
shows input voltage v(in) increasing linearly while output voltage v(out) remains constant at a low potential (~0.0 v) until input voltage v(in) reaches a particular threshold level (~1.1 v) whereupon output voltage v(out) rises suddenly and sharply (~1.5 v). Corresponding to the transition from a low to high voltage level, a significant current i(mn
3
) flows via intermediate transistor MN
3
as indicated in
FIG. 3
b.
FIG. 4
a
shows a block diagram of a Current Mode Dual Trip Point design (a.k.a the Intel 82801BA circuit or I/O Controller Hub2 or South Bridge) for reducing dynamic power dissipation in a bistable pulse generator circuit. Current Mode circuit
4000
includes bias circuit
4900
, low trip point inverter
4100
, high trip point inverter
4200
, tri-state inverter
4300
, weak intermediate inverter
4400
, and 2-stage output buffer
4500
. Low trip inverter
4100
includes load network
4101
coupled to bias circuit
4900
and logic network
4102
coupled to input IN. High trip point inverter
4200
includes load network
4201
coupled to the bias circuit
4900
and logic network
4202
coupled to input IN.
FIG. 4
b
shows a transistor level diagram of the Current Mode Dual Trip Point design. In particular, the circuit shown in
FIG. 4
b
uses pseudo N-MOS arranged circuitry (transistors MPP
1
, MPP
2
, MNP
1
, MNP
2
) to control the current during a low phase operation and pseudo P-MOS arranged circuitry (transistors MPN
1
, MNN
1
, MNN
2
) to control the current during a high phase operation. In particular, transistor MPP
1
serves as a load network and transistors MPP
2
, MNP
1
, MNP
2
serve as a logic network. Transistor MPN
1
serves as a load network and transistors MNN
1
, MNN
2
serve as a logic network.
The pseudo N-MOS arranged circuitry acts as a low trip point buffer
4100
changing its output voltage level at particular low input voltage level while the pseudo P-MOS arranged circuitry acts as a high trip point buffer
4200
changing its output voltage level at a particular low input voltage level. Dynamic power dissipation is reduced because load network resistance may be controlled. However, with this design there is unwanted static power dissipation due to the presence of bias circuit
4900
which consumes static current, as well as pseudo NMOS/PMOS arranged circuitry of high trip point inverter
4200
and pseudo PMOS arranged circuitry of low trip point inverter
4100
.
FIG. 5
a
shows the voltage characteristic of Current Mode circuit
4000
during a high to low transition.
FIG. 5
b
demonstrates the current consumption of Current Mode circuit
4000
during this same period.
FIG. 5
a
shows input voltage v(in) decreasing linearly while output voltage v(out) remains constant at a high potential (~1.5 v) until input voltage v(in) reaches a particular threshold level (~0.4 v) whereupon output voltage v(out) drops suddenly and sharply (~0.0 v).
FIG. 5
b
demonstrates that overall current consumption i(vss) during the high to low transition is reduced as compared with Schmidt Trigger circuit
1000
. However, this overall current consumption i(vss) exists regardless of whether circuit
4000
is in the high to low transition state or merely in the steady state. Such steady state current is consumed by bias circuitry
4900
represented by currents i(mnb
1
) and i(mnb
2
), pseudo NMOS circuitry
4100
represented by current i(mnn
2
), and pseudo PMOS circuitry
4200
represented by current i(mnp
2
).
FIG. 6
a
shows input voltage v(in) increasing linearly while output voltage v(out) remains constant at a low potential (~0.0 v) until the input voltage v(in) reaches a particular threshold level (~0.9 v) whereupon output voltage v(out) rises suddenly and sharply (~1.5 v).
FIG. 6
b
demonstrates that overall current consumption i(vss) during the low to high transition is reduced as compared with Schmidt Trigger circuit
1000
. However, this overall current consumption i(vss) exists regardless of whether circuit
4000
is in the low to high transition state or merely in the steady state. Such steady state current is consumed by bias circuitry
4900
by currents i(mnb
1
) and i(mnb
2
), pseudo NMOS circuitry
4100
represented by current i(mnn
2
), and pseudo PMOS circuitry
4200
represented by current i(mnp
2
).
REFERENCES:
patent: 4539489 (1985-09-01), Vaughn
patent: 6388488 (2002-05-01), Ho
patent: 6433602 (2002-08-01), Lall et al.
Intel Corporation
Kenyon & Kenyon
Le Don
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