Low power driver design

Details Low power driver design Low power driver design

2000-06-02

2002-03-19

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S269000, C327S271000, C327S108000, C326S086000, C326S026000, C326S083000

Reexamination Certificate

active

06359477

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is integrated circuit design and especially low power driver design.
BACKGROUND OF THE INVENTION
Control logic consumes a large percentage of power in today's microprocessors and microcontrollers. A significant amount of this control logic power is consumed by the storage elements. These are typically edge-triggered D flip-flops. Simulations conducted on a microcontroller family estimates that a 30% reduction in flip-flop power consumption translates to about 6% power reduction for the entire integrated circuit. This is the greatest power reduction of all hardware techniques identified. Gated clock methodology translates to only less than 2% saving of the total integrated circuit power. Therefore it is essential that the library of design cells for low power application specific integrated circuits (ASIC's) include low power versions of the flip-flops.
SUMMARY OF THE INVENTION
A buffer circuit includes a chain of a plurality of inverters. A first inverter has transistors with a size to present a first predetermined capacitive loading at its input. This is selected with regard to the target operating frequency of the driving circuit (typically a flip-flop) and the transistor size selected for this driving circuit. Each inverter has transistors with a size a predetermined size factor greater than the transistors of a preceding inverter. The first inverter has transistors the size factor larger than the driving circuit. The size factor is preferably 3. The number of inverters in the chain is selected so that the last inverter has transistors with a size to drive its output capacitive loading with a maximum rise and fall time corresponding to the target frequency. If the number of inverters is even, then the buffer input is connected to a normal output of the driving circuit. If the number of inverters is odd, then the buffer input is connected to an inverted output of the driving circuit.


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patent: 5973509 (1999-10-01), Taniguchi et al.
patent: 5986463 (1999-11-01), Takiguchi
patent: 6160742 (2000-12-01), Chung et al.

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