Low-power DRAM and method for driving the same

Details Low-power DRAM and method for driving the same Low-power DRAM and method for driving the same

2007-10-23

2010-10-26

Le, Vu A (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S230080, C365S230010

Reexamination Certificate

active

07821812

ABSTRACT:
A dynamic random access memory includes: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row address; an enabler configured to decode a part of most significant bits (MSB) of the column address to locally enable a part of one page area corresponding to the row address; and a column decoder configured to decode the column address.

REFERENCES:
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patent: 6230250 (2001-05-01), Vogley
patent: 6243320 (2001-06-01), Hamamoto et al.
patent: 2004/0213036 (2004-10-01), Farrell et al.
patent: 2006/0067151 (2006-03-01), Miyamoto
patent: 10-0183538 (1998-12-01), None
patent: 10-2000-0026252 (2000-05-01), None
patent: 1020050065269 (2005-06-01), None
Korean Office Action, with English Translation, issued in Korean Patent Application No. KR 10-2007-0106069, dated Dec. 3, 2008.
Notice of Allowance issued from Korean Intellectual Property Office on May 30, 2009 with an English Translation.
Office Action from German Patent and Trademark Office on Sep. 4, 2009 with an English Translation.
Dave Bursky, “Synchronous DRAMS Clock At 100 MHZ,” Electronic Design, Feb. 18, 1993, pp. 45,46,48 and 49.

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