Low-power-dissipation CMOS circuits

Details Low-power-dissipation CMOS circuits Low-power-dissipation CMOS circuits

1994-12-02

1996-03-26

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 98, 327544, H03K 190948

Patent

active

055024076

ABSTRACT:
In low-power-dissipation CMOS circuitry, conventional CMOS inverters are powered by a repetitively ramped power supply. Clock signals are needed in the circuitry for controlling data flow therein. To ensure optimal low-power operation of the circuitry, clock signals are derived directly from the ramped power supply waveform itself. Additionally, a technique similar to that employed in the clock-signal-generating arrangement is utilized to propagate digital data signals between chips in a low-power way.

REFERENCES:
patent: 3983412 (1976-09-01), Roberts et al.
Seitz et al.; "Hot-Clock nMOS"; published 1, Proceedings of the 1985 Chapel Hill Conference on VLSI, Computer Science Press, 1985.
Younis et al.; "Practical Implematation at Charge Recovering Asymptotically Zero Power CMOS", Artificial Intelligence Lab., Massachusetts Institute of Technology; Oct. 9, 1992.
T. Gabara, "Pulse Power Supply--PPS CMOS", 1994 IEEE Symposium on Low Power Electronics, pp. 98-99.

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