Low-power-dissipation CMOS circuits

Details Low-power-dissipation CMOS circuits Low-power-dissipation CMOS circuits

1994-04-08

1995-09-12

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326121, 327544, H03K 1920

Patent

active

054500273

ABSTRACT:
A conventional CMOS inverter circuit is operated in a low-power-dissipation mode by being connected to a pulsed power supply. The circuit is utilized as a basic building block to realize a variety of logic and memory functions.

REFERENCES:
patent: 5324992 (1994-06-01), Maly
patent: 5329169 (1994-07-01), Ihara
C. L. Seitz et al, "Hot-Clock nMOS", 1985, pp. 1-17, Proceedings of the 1985 Chapel Hill Conference on VLSI, Computer Science Press.

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