Low power display refresh

Details Low power display refresh Low power display refresh

2003-04-03

2010-06-08

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000

Reexamination Certificate

active

07734943

ABSTRACT:
An application processor coupled to a Static Random Access Memory (SRAM) interfaces with a graphics accelerator. A Dynamic Random Access Memory (DRAM) stores frame buffer data that may be transferred to a display through a switch located on the graphics accelerator in normal operation. In a power savings mode, the DRAM may be powered down and a copied frame buffer data stored in the SRAM may be transferred to the display through the switch.

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