Low power differential receiver input circuit

Details Low power differential receiver input circuit Low power differential receiver input circuit

1994-09-07

1996-01-23

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 83, 327203, H03K 190185, H03K 190948

Patent

active

054867770

ABSTRACT:
A low power differential receiver input stage using n-channel/p-channel transistor pairs to adjust the voltage levels of differential output signals. A first n-channel/p-channel transistor pair is connected to a first output terminal and a second n-channel/p-channel transistor pair is connected to a second output terminal. First and second differential signals respectively applied to first and second input terminals are passed to the first and second output terminals through first and second resistors, respectively. The first differential signal is applied to the gates of the second n-channel/p-channel transistor pair, thereby adjusting the voltage level at the second output terminal. Similarly, the second differential signal is applied to the gates of the first n-channel/p-channel transistor pair, thereby adjusting the voltage level at the first output terminal.

REFERENCES:
patent: 3763384 (1973-10-01), Stutz
patent: 3982196 (1976-09-01), Poujouis
patent: 4785299 (1988-11-01), Trumpp
patent: 4809226 (1989-02-01), Ochoa, Jr.
patent: 4890010 (1989-12-01), Neudeck et al.
patent: 5140179 (1992-08-01), Takano
patent: 5173870 (1992-12-01), Sukashita et al.

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