Low power delay controlled zero sensitive sense amplifier

Details Low power delay controlled zero sensitive sense amplifier Low power delay controlled zero sensitive sense amplifier

2006-10-31

2006-10-31

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S207000

Reexamination Certificate

active

07130236

ABSTRACT:
In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole coupled to a positive power supply. The second transfer gate has a first pole coupled to a bitline of the memory cell. The comparator has a first input coupled to a second pole of the first transfer gate, a second input coupled to a second pole of the second transfer gate, and an output coupled to the second input. The comparator compares signals on the first and second inputs and selectively generates a greater differential signal there-between. The control circuit turns off the comparator responsive to a logical zero being read from the memory cell avoiding the generation of the greater differential signal.

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Yen-Jen Chang et al., “Value-Conscious Cache: Simple Technique for Reducing Cache Access Power,” Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2004 IEEE, all pages.

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