Low-power delay buffer circuit

Details Low-power delay buffer circuit Low-power delay buffer circuit

2007-01-30

2007-01-30

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S189120

Reexamination Certificate

active

11124999

ABSTRACT:
A low-power delay buffer circuit is provided, which utilizes a ring counter as address decoder and a latch array for memory. To reduce power consumption, a gated-clock driver tree is applied to the ring-counter addressing architecture. Moreover, a similar gated-driver tree is applied to the input and output ports of the latch array. The delay buffer circuit not only could achieve a power consumption lower than SRAM-based delay buffers, but also could operation under high frequencies and take up less layout area than SRAM-based delay buffers.

REFERENCES:
patent: 2002/0000855 (2002-01-01), Lee

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