Low-power decoder for selecting redundant memory cells

Details Low-power decoder for selecting redundant memory cells Low-power decoder for selecting redundant memory cells

1993-02-17

1994-08-09

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 365227, 36523006, 3652257, G11C 1300

Patent

active

053372786

ABSTRACT:
To avoid unnecessary power dissipation, a decoder for selecting redundant memory cells in a memory device provides, for each section of the memory device, a first node and a second node that are coupled through a fuse-programmable ROM. If a defective memory cell is found in a section of the memory device, the fuse-programmable ROM of that section is programmed so as to decouple the first node from the second node when the defective memory cell is addressed. Prior to every access cycle, the first and second nodes of all sections are precharged. When address signals are received, the second node of the addressed section is discharged, other second nodes remaining charged. Normal or redundant memory cells are selected by performing a logic operation on the potentials of the first nodes.

REFERENCES:
patent: 4689494 (1987-08-01), Chen et al.
patent: 4860260 (1989-08-01), Saito et al.
patent: 4951253 (1990-08-01), Sahara et al.
patent: 4985866 (1991-01-01), Nakaizumi
patent: 5058059 (1991-10-01), Matsuo et al.

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