Low power content addressable memory architecture

Details Low power content addressable memory architecture Low power content addressable memory architecture

2002-04-30

2003-06-24

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S203000

Reexamination Certificate

active

06584003

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memories (CAM). More particularly the invention relates to a CAM architecture for reducing power consumption.
BACKGROUND OF THE INVENTION
In many conventional memory systems, such as random access memory, binary digits (bits) are stored in memory cells, and are accessed by a processor that specifies a linear address that is associated with the given cell. This system provides rapid access to any portion of the memory system within certain limitations. To facilitate processor control, each operation that accesses memory must declare, as a part of the instruction, the address of the memory cell/cells required. Standard memory systems are not well designed for a content based search. Content based searches in standard memory require software based algorithmic search under the control of the microprocessor. Many memory operations are required to perform a search. These searches are neither quick nor efficient in using processor resources.
To overcome these inadequacies an associative memory system called Content Addressable Memory (CAM) has been developed. CAM allows cells to be referenced by their contents, so it has first found use in lookup table implementations such as cache memory subsystems and is now rapidly finding use in networking systems. CAM's most valuable feature is its ability to perform a search and compare of multiple locations as a single operation, in which search data is compared with data stored within the CAM. Typically search data is loaded onto search lines and compared with stored words in the CAM. During a search-and-compare operation, a match or mismatch signal associated with each stored word is generated on a matchline, indicating whether the search word matches a stored word or not. A typical word of stored data includes actual data with a number appended header bits, such as an “E” bit or empty bit for example, although the header bits are not specifically searched during search-and-compare operations.
A CAM stores data in a matrix of cells, which are generally either SRAM based cells or DRAM based cells. Until recently, SRAM based CAM cells have been most common because of their simple implementation. However, to provide ternary state CAMS, ie. where each CAM cell can store one of three values: a logic “0”, “1” or “don't care” result, ternary SRAM based cells typically require many more transistors than ternary DRAM based cells. As a result, ternary SRAM based CAMs have a much lower packing density than ternary DRAM based cells.
A typical CAM block diagram is shown in FIG.
1
. The CAM
10
includes a matrix, or array
25
, of DRAM based CAM cells (not shown) arranged in rows and columns. An array of DRAM based ternary CAM cells have the advantage of occupying significantly less silicon area than their SRAM based counterparts. A predetermined number of CAM cells in a row store a word of data. An address decoder
17
is used to select any row within the CAM array
25
to allow data to be written into or read out of the selected row. Data access circuitry such as bitlines and column selection devices, are located within the array
25
to transfer data unto and out of the array
25
. Located within CAM array
25
for each row of CAM cells are matchline sense circuits, which are not shown, and are used during search and compare operations for outputting a result indicating a successful or unsuccessfully match of a search word against the stored word in the row. The results for all rows are processed by the priority encoder
22
to output the address (Match Address) corresponding to the location of a matched word. The match address is stored in match address registers
18
before being output by the match address output block
19
. Data is written into array
25
through the data I/O block
11
and the various data registers
15
. Data is read out from the array
25
through the data output register
23
and the data I/O block
11
. Other components of the CAM include the control circuit block
12
, the flag logic block
13
, the voltage supply generation block
14
, various control and address registers
16
, refresh counter
20
and JTAG block
21
.
FIG. 2
depicts a hierarchical view of the typical CAM array
25
. CAM array
25
includes a matrix of CAM cells
30
and a matchline sense circuit block
26
. CAM cells
30
of the CAM array
25
are arranged in rows and columns. CAM cells
30
of a row are connected to a common matchline MLi, word line WLi and tail line TLi, and CAM cells
30
of a column are connected to a common pair of search lines SLj*/SLj and a common pair of bitlines BLj/BLj*, where i is an integer value between 0 and n, and j is an integer value between 0 and m. Located adjacent to the CAM array
25
for each row is matchline sense circuit block
26
. Matchline sense circuit block
26
includes one matchline sense circuit
27
connected to a respective matchline MLi, and is used during search-and-compare operations for outputting match signals ML OUTO-ML OUTn which indicate a successful or unsuccessful match of a search word against the stored word. Matchlines MLi and tail lines TLi are connected to their respective matchline sense circuits
27
, and tail lines TLi can be selectively connected to ground potential. Although not shown in the simplified schematic of
FIG. 2
, the matchline sense circuits
27
also receive control signals to control their operation, and a person skilled in the art would understand that such control signals to be necessary for their proper operation of the circuit.
FIG. 3
shows a typical ternary DRAM type CAM cell
30
as described in issued U.S. Pat. No. 6,320,777 B1. Cell
30
has a comparison circuit which includes an n-channel search transistor
31
connected in series with a n-channel compare transistor
32
between a matchline ML and a tail line TL. A search line SL* is connected to the gate of search transistor
31
. The storage current includes a n-channel access transistor
33
having a gate connected to a wordline WL and connected in series with capacitor
34
between bitline BL and a cell plate voltage potential VCP. Charge storage node CELL
1
is connected to the gate of compare transistor
32
to turn on transistor
32
if there is charge stored on capacitor
34
i.e. if CELL is logic “I”. The remaining transistors and capacitor replicate transistors
31
,
32
,
33
and capacitor
34
for the other half of the ternary data bit, and are connected to corresponding lines SL and BL* and are provided to support ternary data storage. Together they can store a ternary value representing logic “1”, logic “0”, or “don't care”.
Ternary Value
CELL 1
CELL 2
0
0
1
1
1
0
“Don't Care”
0
0
The tail line TL is typically connected to ground and all the transistors are n-channel transistors. The description of the operation of the ternary DRAM cell is detailed in the aforementioned issued patent 6,322,771 B1.
As matchlines become longer with increasing memory densities, so does the parasitic capacitance for the longer matchlines. The additional loading of the matchlines due to the increased parasitic capacitance presents several design problems associated with matchline sensing. First, the current of a single conduction path produced by a non-match CAM cell between the matchline and VSS is approximately 10 &mgr;A. Hence the matchline sense amplifier must be sensitive enough to detect this small current. Second, the operating frequency of the CAM chip should be high, in other words, the working cycle of the matchline sense amplifier should be as short as possible to attain high CAM performance. Third, because all matchlines of the CAM chip are active at the same time during search-and-compare operations, the matchline voltage swing should be kept as low as possible to minimize power dissipation. Fourth, sensing should be stable and have good sensing margins for reliable sensing. Fifth, the matchline sense amplifier circuit should be simple and small enough to fit into a tight pitch CAM core layout to minimize are

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