Low power consumption designing method of semiconductor...

Details Low power consumption designing method of semiconductor... Low power consumption designing method of semiconductor...

2006-01-06

2008-08-05

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07409650

ABSTRACT:
In a standard cell synthesizing step101, a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register description portion with an instance name contained in the net list; in a simulation step103, an operation simulation written by the RTL description is carried out; the toggle information among registers which is extracted in the simulation step103is recorded in a toggle storing step104, a flip-flop-to-flip-flop toggle information database is constructed in which the recorded toggle information corresponds to a flip-flop-to-flip-flop instance name obtained from the instance name list in a mapping step105; and in an electric power optimizing step102, a physical designing operation for reducing power consumption is optimized by employing the net list, the flip-flop-to-flip-flop toggle information database, and a timing restriction.

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Japanese Office Action issued in Japanese Patent Application No. JP 2005-002426, dated Apr. 2, 2008.

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