Low power consumption data processing system

Details Low power consumption data processing system Low power consumption data processing system

1979-10-30

1982-02-16

Shaw, Gareth D.

Boots, shoes, and leggings

364707, 365227, 365228, G06F 100, H03K 2130

Patent

active

043162479

ABSTRACT:
A data processing system which contains a read-only memory circuit, an arithmetic circuit, and a control circuit on a single semiconductor chip including a clock generating circuit for supplying system clocks to all of the circuits on the chip and the clock generating circuit is structured such that on the input of an external halt signal, the clock circuits will cease supplying system clocks during a period that provides for information contained within the system on the semiconductor chip.

REFERENCES:
patent: 3941989 (1976-03-01), McLaughlin et al.
patent: 3991305 (1976-11-01), Caudel et al.
patent: 4137563 (1979-01-01), Tsunoda
patent: 4151611 (1979-04-01), Sugawara
patent: 4164666 (1979-08-01), Hirasawa
patent: 4218876 (1980-08-01), Hashimoto et al.
patent: 4240150 (1980-12-01), Ebihara et al.
"A Monostable CMOS RAM with Self-Refresh Mode", by Shiga et al., IEEE Journal of Solid-State CKT, vol. SC-11, No. 5, Oct. 76, pp. 609-613.
"Dynamic Refresh for Random Access Memory", Anon., Electronic Engineering, vol. 48, No. 583, p. 19, Sep. 1976.

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