Low power consuming circuit

Details Low power consuming circuit Low power consuming circuit

2001-07-03

2002-11-05

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S121000, C326S033000, C326S017000, C327S544000

Reexamination Certificate

active

06476641

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit made up of a CMIS (Complementary Metal Insulator Semiconductor) providing a low threshold voltage and more particularly to a low power consuming circuit enabling reduction in power consumption during standby (that is, while in a standby mode).
The present application claims priority of Japanese Patent Application No. 2000-200643 filed on Jul. 3, 2000, which is hereby incorporated by reference.
2. Description of the Related Art
As is well known in this technical field, a layer-stacked structure made up of a metal, an insulator (thin insulating film), and a semiconductor, with the insulator interposed between the metal and the semiconductor, is called a “MIS” structure. A MIS-type field effect transistor using a silicon oxide film as the insulator is called a MOS (Metal Oxide Semiconductor) field effect transistor. Hereinafter the field effect transistor is referred to as an FET or simply as a transistor. The MIS transistor provides a threshold voltage (hereinafter referred to simply as a “Vt”).
By causing the Vt to be lowered, even when a low voltage is supplied, the MIS transistor can be operated at a high speed. However, as shown in
FIG. 4
, it is known that, if the Vt in the MIS transistor is lowered, when an enhancement type MIS transistor is turned OFF (that is, when the gate voltage is 0V), sub-threshold leakage currents between a drain and a source are increased. For example, when a thickness of an oxide film is 60 Å and a temperature is 85° C., every time the Vt is decreased by 100 mV, drain current increases by ten times.
On the other hand, if the Vt is increased, a junction leakage current (being dependent on drain voltage) between the drain and a back gate becomes predominant as the transistor drains leakage current, causing the transistor to be saturated.
Moreover, if a supply voltage is lowered, the junction leakage current is decreased, however, if the supply voltage is lowered without changing dimensions of the transistor, operation speed of the transistor decreases. To increase the operation speed with the supply voltage being lowered, an increase in size of the transistor is required. However, when the transistor is increased in size, since a parasitic capacitance is increased, the operation speed is not always made high unconditionally.
Therefore, reducing of a thickness of a gate oxide film or lowering of the Vt is effective for operating the transistor at high speed even while a low voltage is supplied without increasing the transistor in size. However, to reduce the leakage current, it is necessary to make the Vt high. Because of this, conditions for the Vt to achieve high operations at the time of supply of low voltages and simultaneously to lower power consumption are mutually exclusive.
To solve this problem, a method is proposed in which power consumption is lowered as a whole and high speed operations are assured by switching between a high speed operation mode (active mode) and a low power consumption mode (standby mode) in terms of time. To implement this, technology in which the Vt can be changed in terms of time is required.
FIG. 5
is a diagram showing a conventional low power consuming circuit. The low power consuming circuit shown in
FIG. 5
includes a low threshold logic circuit
3
and an N-channel transistor source voltage generating circuit
8
.
As shown in
FIG. 5
, the low threshold logic circuit
3
is a CMIS standard inverter circuit made up of a P-channel MIS transistor
31
and an N-channel MIS transistor
32
. A gate of the P-channel MIS transistor
31
is connected to a gate of the N-channel MIS transistor
32
. A drain of the P-channel MIS transistor
31
is connected to a drain of the N-channel MIS transistor
32
. The gates of the P-channel MIS transistor
31
and of the N-channel MIS transistor
32
are connected to an input terminal “IN” and their drains are connected to an output terminal “OUT”. A back gate and a source of the P-channel MIS transistor
31
are connected to each other and the source of the P-channel MIS transistor
31
is connected to a power source terminal VDD. A source of the N-channel MIS transistor
32
is connected to a grounding terminal GND and a back gate of the N-channel MIS transistor
32
is connected to the grounding terminal GND. The power source terminal VDD is also called a maximum power source and the grounding terminal GND is also called a minimum power source.
On the other hand, the N-channel transistor source voltage generating circuit
8
is made up of an N-channel MIS transistor
81
and a diode
82
. The N-channel MIS transistor
81
acts as a switch N-channel transistor. A drain of the N-channel MIS transistor
81
is connected to the power source terminal VDD and its back gate is connected to the grounding terminal GND. A gate of the N-channel MIS transistor
81
is connected to a control terminal STB. A source of the N-channel MIS transistor
81
is connected to an anode of the diode
82
. A cathode of the diode
82
is connected to the grounding terminal GND.
The source of the N-channel MIS transistor
32
in the low threshold logic circuit
3
is connected to the anode of the diode
82
in the N-channel transistor source voltage generating circuit
8
and to the source of the N-channel MIS transistor
81
.
Another related art is also known. For example, a “semiconductor integrated circuit” is disclosed in Japanese Patent Application Laid-open No. 2000-13215 (hereinafter referred to as a “prior art 1”) in which a leakage current during standby in a logic circuit including a low threshold complementary type FET can be reduced by using simple configurations of the logic circuit and, at the same time, a potential at each node is still maintained during standby. In the prior art 1, switching of two kinds of source voltages is implemented by connecting, in parallel, a potential clamping circuit made up of a diode, a high resistance device or a transistor, and a control transistor. Moreover, in the prior art 1, the switching is implemented by switching between two modes in a configuration in which two devices are connected in parallel and in a configuration in which devices of the same kind are connected in serial.
Next, operations of a low power consuming circuit disclosed in the prior art 1 will be described by referring to FIG.
6
. The low power consuming circuit in
FIG. 6
includes a low threshold logic circuit
3
, first voltage clamping diode (potential clamping circuit)
10
, P-channel transistor source voltage switching transistor (control transistor)
11
, a second voltage clamping diode (potential clamping circuit)
12
, and N-channel transistor source voltage switching transistor (control transistor)
13
.
As shown in
FIG. 6
, to a source of a P-channel MIS transistor
31
in the low threshold logic circuit
3
is connected the first voltage clamping diode
10
and the P-channel transistor source voltage switching transistor
11
in parallel so that the P-channel MIS transistor
31
is forward-biased from a power source VDD. That is, an anode of the first voltage clamping diode
10
is connected to the power source VDD and a cathode of the first voltage clamping diode
10
is connected to the source of the P-channel MIS transistor
31
in the low threshold logic circuit
3
. The P-channel transistor source voltage switching transistor
11
is made up of a P-channel MIS transistor
111
. A back gate and a source of the P-channel MIS transistor
111
are connected to each other and its source is connected to the power source VDD. A gate of the P-channel MIS transistor
111
is connected to a first control terminal STB and its drain is connected to the source of the P-channel MIS transistor
31
in the low threshold logic circuit
3
.
On the other hand, to a source of a N-channel MIS transistor
32
in the low threshold logic circuit
3
is connected the second voltage clamping diode
12
and the N-channel transistor source voltage switching transistor

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