Low-power CMOS device and logic gates/circuits therewith

Details Low-power CMOS device and logic gates/circuits therewith Low-power CMOS device and logic gates/circuits therewith

2000-06-21

2002-08-06

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S371000, C257S373000

Reexamination Certificate

active

06429492

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a low-power CMOS device and logic gates/circuits therewith and, more particularly, to electrical circuits having enhanced noise tolerance.
BACKGROUND ART
Complementary metal-oxide-semiconductor (CMOS) devices and circuitry are used extensively to implement digital logic circuits. CMOS circuitry exhibits two exemplary characteristics: low-power consumption and high noise tolerance.
Because of these characteristics and because such circuitry is relatively inexpensive to fabricate and has relatively high reliability, CMOS devices, rather than bipolar and N-type MOS transistors, are predominately used to make integrated circuits.
The elemental CMOS circuit is a conventional CMOS inverter
100
, illustrated in FIG.
1
A. The CMOS inverter
100
includes a N-type MOS field effect transistor (N-MOSFET)
120
and a P-type MOS field effect transistor (P-MOSFET)
140
coupled in series. The gate electrodes
160
and
180
, respectively, of the N-MOSFET
120
and the P-MOSFET
140
are coupled together to form the input
190
of the conventional CMOS inverter
100
. Drain/source nodes of the N-MOSFET
120
and P-MOSFET
140
are coupled together to form the output
170
of the conventional CMOS inverter
100
. The other source/drain nodes and the body connections of the P-MOSFET
140
and the N-MOSFET
120
device are respectively coupled to a supply voltage V
dd
130
and to ground (GND)
150
. As used herein, the terms source/drain (and drain/source) are used to refer to both drain and source regions of MOSFET transistors. This nomenclature reflects the interchangeability of the drain and source regions in a MOSFET device, where a particular designation of source or drain depends on the voltages applied to each of these regions.
Operation of the conventional CMOS inverter
100
is well known to persons skilled in the art of circuit design. The corresponding voltage transfer characteristic (VTC)
101
(i.e., V
out
versus V
in
plot) for the conventional CMOS inverter
100
is illustrated in idealized form in FIG.
1
B. The VTC
101
includes four operating regimes, I, II, III, IV, that occur when switching from one logic state to the other. In regime I, the P-MOSFET is ON and the N-MOSFET is OFF, in region II, the P-MOSFET is in its linear region while the N-MOSFET is in saturation, in region III, the P-MOSFET is in saturation while the N-MOSFET is in its linear region, and, lastly, in region IV, the P-MOSFET is OFF and the N-MOSFET is ON. At the transition between regimes II and III, both the N-MOSFET and the P-MOSFET are simultaneously conducting; as discussed below, it is at this transition that the circuit is momentarily short-circuited between V
dd
and circuit ground
150
. The VTC
101
of the conventional CMOS inverter
100
illustrates that the voltage logic level at the output
170
is the logical inverse of the voltage logic level at the input
190
.
At least three sources of power dissipation exist in a CMOS circuit, such as the conventional CMOS inverter
100
of FIG.
1
A:
(1) switching power dissipation;
(2) short-circuit power dissipation; and
(3) static power dissipation resulting from reverse-biased PN junction leakage currents.
The switching power is the power dissipated each full cycle due to the successive charging and discharging of the capacitive load tied to the output node of a CMOS circuit (e.g., output
170
of the conventional CMOS inverter
100
). Switching power is generally the largest component of total CMOS circuit power dissipation. CMOS circuit switching power consumption may be significantly reduced by diminishing the load capacitance coupled to the output of the CMOS circuit. Such load capacitance is typically the input capacitance of a successively coupled CMOS circuit. CMOS circuit input capacitance (e.g., load capacitance) is principally reduced by reducing MOSFET gate lengths in the CMOS circuits.
Short-circuit power consumption is the momentary direct-path DC power that is dissipated by the CMOS circuit each time its logic input conditions cause its output to change from one logic state to the other logic state. Short-circuit power consumption is due to the short-circuit path that arises at the transition between regimes II and III in
FIG. 1B
during output state changes when the serially coupled N-MOSFET
120
and P-MOSFET
140
are simultaneously conductive (e.g., turned ON), so that current flows from a power supply V
dd
to ground
150
. During this conduction period (i.e., when both MOSFETs
120
,
140
are simultaneously substantially turned ON), short-circuit power is dissipated in the MOSFETs output conductances and parasitic resistances. While the conduction period for short-circuit current is very short for each logic state transition, at higher switching speeds, the conduction period can become a successively higher and more significant fraction of the clock cycle resulting in significant short-circuit power dissipation.
Finally, static leakage power consumption is due to the small leakage currents that arise from reverse-biased PN junctions (and sub-threshold effects). Static leakage power consumption is generally the smallest component of total CMOS circuit power dissipation.
In addition to their relatively low power consumption, CMOS circuits, operating at conventional supply voltages (e.g., five volts), have relatively high noise tolerance, and thus are more accepting of variations in input signal levels.
The high noise tolerance of CMOS circuits better assures the accuracy of CMOS circuit signal processing, even in relatively noisy environments.
Having a relatively high noise tolerance permits a CMOS circuit to interpret input signals within a relatively large voltage range near either logic state voltage (e.g., outside a relatively small range approximately centered at one-half the power supply voltage) as either a logic ‘0’ or as a logic ‘1’. This ability allows CMOS circuitry to better tolerate noise, for example, generated within or outside of the CMOS circuitry as will be later described.
Such enhanced noise tolerance for CMOS circuitry may be quantified by a measures known as noise margins.
FIG. 1B
illustrates four output and input voltage levels, of the conventional CMOS inverter
100
, used to quantify noise tolerance.
1. V
oh
=Minimum logic ‘1’ output voltage (
20
)
2. V
ol
=Maximum logic ‘0’ output-voltage (
40
)
3. V
ih
=Minimum input voltage recognized as logic ‘1’ (
80
)
4. V
il
=Maximum input voltage recognized as logic ‘0’ (
60
)
Typically, V
oh
20
equals the supply voltage (V
dd
)
130
and V
ol
40
equals zero volts, or ground (GND)
150
.
Two noise margins (respectively, for the high, or logic ‘1’, and low, or logic ‘0’, states) may be defined as follows:
1. Noise Margin High: NM
H
=V
oh
−V
ih
2. Noise Margin Low: NM
L
=V
il
−V
ol
High noise margins, or tolerance to variations in the signal level, are especially valuable in environments having circuit noise that can significantly corrupt signals. The circuit noise may be undesirable signals coupled to the CMOS circuit. Such circuit noise may be coupled from neighboring transmission lines (e.g., in a highly integrated circuit) or coupled from other sources by capacitive or inductive coupling. Such noise may cause the voltage level at a node in a CMOS circuit to significantly vary, potentially affecting the logic states at that and other circuit nodes. The high noise tolerance of CMOS circuits generally ensures that both noisy and noiseless input signals presented to a CMOS circuit are interpreted properly.
Because transistor dimensions are continuing to decrease, the density (e.g., device density) of CMOS integrated circuits continues to increase. As a result, CMOS circuit noise margins are undesirably declining as device density increases.
Increased density increases the power dissipation per unit area of CMOS circuits; increased power dissipation may diminish CMOS circuit reliability.
Further, the power consumption of highly integrated CMOS circuits

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