Low-power clock/calendar architecture

Details Low-power clock/calendar architecture Low-power clock/calendar architecture

1988-10-28

1992-12-29

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG2, G06F 1520, G06F 1300

Patent

active

051756994

ABSTRACT:
An integrated circuit timekeeper, which uses a hybrid hardware/software architecture, wherein the least significant bits are updated in hardware and the more significant bits are updated in software. This hybrid architecture provides improved power efficiency, layout efficiency, and flexibility in reconfiguration.

REFERENCES:
patent: 4088990 (1978-05-01), Sass
patent: 4301524 (1981-11-01), Koepp et al.
patent: 4379339 (1983-04-01), Narita
patent: 4385841 (1983-05-01), Kramer
patent: 4386423 (1983-05-01), Sasaki et al.
patent: 4427299 (1984-01-01), Hasegawa
patent: 4444512 (1984-04-01), Piguet et al.
patent: 4677541 (1987-06-01), Singhi
patent: 4852030 (1989-07-01), Munday
patent: 4930100 (1990-05-01), Morinaga et al.
patent: 5050113 (1991-09-01), Podkowa et al.
Data sheet from the 1987 Data Book of Dallas Semiconductor, Inc. describing the "DS1215" part, pp. 193-208.

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