Low power circuits through hazard pulse suppression

Details Low power circuits through hazard pulse suppression Low power circuits through hazard pulse suppression

1997-05-30

1999-11-09

Teska, Kevin J.

39550003, G06F 1750

Patent

active

059830077

ABSTRACT:
The power dissipation in a circuit, e.g., a CMOS circuit, is reduced through hazard pulse suppression. More particularly, hazard-producing gates are those gates whose delays are smaller than the differential path delays for their inputs. The adjustment to the delay of these gates is made by increasing the gate delay as a function of the corresponding differential path delays to eliminate the production of hazard pulses. Thus, by suppressing the hazard pulses in a circuit the power dissipation of the circuit is substantially reduced.

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