Low-power cache system and method

Details Low-power cache system and method Low-power cache system and method

2000-05-01

2009-02-03

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C711S118000

Reexamination Certificate

active

07487369

ABSTRACT:
The invention provides a cache architecture that selectively powered-up a portion of data array in a pipelined cache architecture. A tag array is first powered-up, but the data array is not powered-up during this time, to determine whether there is a tag hit from the decoded index address comparing to the tag compare data. If there is a tag hit, during a later time, a data array is then powered-up at that time to enable a cache line which corresponds with the tag hit for placing onto a data bus. The power consumed by the tag represents a fraction of the power consumed by the data array. A significant power is conserved during the time in which the tag array is assessing whether a tag hit occurs while the data array is not powered-on at this point.

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patent: 6601155 (2003-07-01), Krimer et al.
patent: 04186595 (1992-07-01), None

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