Low-power BiCMOS/ECL SRAM

Details Low-power BiCMOS/ECL SRAM Low-power BiCMOS/ECL SRAM

1995-11-16

1997-02-11

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Semiconductive

36518905, 36518911, 36518908, 365190, 365205, 3652256, 36523006, 36523008, G11C 1140

Patent

active

056027745

ABSTRACT:
A SRAM includes an ECL input buffer connected between an address bus and a W-OR predecoder array. The logic output of the W-OR predecoder array is applied to a level translator array and level shifted. The level shifted output of the level translator array is supplied to a plurality of self-resetting word-line decoder and driver (WLDD) circuits. The WLDD circuits supply activation pulses to selected blocks of memory in a memory cell array. Sense amplifiers sense and latch-in the data stored in the activated selected blocks of memory. The design of the W-OR predecoder array, level translator array, WLDD circuits and sense amplifiers is such to reduce the overall power consumption of the SRAM.

REFERENCES:
patent: 5331219 (1994-07-01), Nakamura

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