Low-power area-efficient and robust asynchronous-to-synchronous

Details Low-power area-efficient and robust asynchronous-to-synchronous Low-power area-efficient and robust asynchronous-to-synchronous

1993-11-30

1996-05-28

Harvey, Jack B.

Pulse or digital communications

Repeaters

Testing

375354, 375362, H04L 700

Patent

active

055220487

ABSTRACT:
An asynchronous to synchronous interface between a master chip and a target chip, the interface being located on the target chip, includes a synchronous write logic unit and one set of synchronous transfer latches. A system clock (clock on target chip) and asynchronous clock signal are connected to the synchronous write logic unit. The asynchronous clock signal is also connected to a set of asynchronous latches, which receive data from the master chip upon receiving active asynchronous clock signals. The asynchronous latches are connected to a set of synchronous latches. The synchronous latches are controlled by a synchronous write signal generated by the synchronous write logic unit. Based on the asynchronous write signal and clock signal of the target chip the synchronous write logic unit synchronously transfers data from the outputs of the asynchronous latches to the outputs of the synchronous latches.

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