Low-power apparatus for power management enabling

Details Low-power apparatus for power management enabling Low-power apparatus for power management enabling

1999-05-28

2002-05-21

Thai, Xuan M. (Department: 2181)

Electrical computers and digital processing systems: support

Computer power control

By external command

C713S323000

Reexamination Certificate

active

06393570

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to techniques for controlling power management functions in computer systems, and more particularly to the problem of maintaining proper power consumption during power management processes.
2. Description of Related Art
The control of power supplied to computer systems is used in many environments. For example, management of computer networks is accomplished in many systems by a central network management station which has access to end stations in the network for management functions. However, in complex network environments, many of the end stations are turned off at night or at other times when they are not in use, either manually or automatically by power management circuits. This prevents the network management station from gaining access to the end station, limiting the ability to effectively manage the network. Thus, technology has evolved which allows a remote network management station to wake-up an end station in the network to allow it to perform network management processes, or otherwise communicate with the end station. Such technology is referred to generally as Wake-On-LAN herein. The Wake-On-LAN feature of network adapter cards in personal computers allows network administrators to remotely boot powered off end systems. One popular technology for implementing the Wake-On-LAN feature is referred to as the “Magic Packet” technology, developed by Advanced Micro Devices, Inc. See “Magic Packet Technology—White Paper” Advanced Micro Devices, Inc., issued November 1995.
One popular bus system used with computer systems that support wake up devices, like Wake-On-LAN network interface cards is known as the PCI Local Bus, or PCI bus. The
PCI Local Bus Specification
, Revision 2.2, (PCI Special Interest Group, Dec. 18, 1998) (herein PCI 2.2) places strict power requirements on wake-up devices in systems using PCI bus compliant buses. According to PCI 2.2, system software is given the job of managing the different power-use states, but an inherent problem arises when a black-out or a momentary loss of power creates a situation in which the software cannot operate as designed. In this case, the wake-up devices may draw more power than the system has available, and at the same time, may not be able to wake-up the computer properly. To ensure proper wake-up operation even after a power loss the hardware must be capable of dealing with the situation.
The
PCI Bus Power Management Interface Specification
, Revision 1.1, PCI Special Interest Group, (Dec. 18, 1998) defines three different power states to be controlled by the operating system. The operating system is given the task of power management since it knows when the system is busy and when it is idle. (See
PCI Bus Power Management Interface Specification
, page 9) Unfortunately the dominating operating systems today (Windows/DOS) are not very stable and are prone to crashes. This unreliability coupled with the fact that an unintentional power cycling may cause the computer to power-up in an is unknown state requires hardware to make allowances to operate properly in the absence of software control.
The different states of power management define the amount and type of activity allowed on the PCI bus for a given state. In the normal process of going into the power-down state (D
3
cold) the operating system enables specific devices to be able to wake up the system on a predefined wake up event by setting a Power Management Enable select PME_En bit in a status register associated with the PCI bus controller. Once at least one device is enabled to wake-up the machine, the system can remove power from the power-rails on the PCI bus. At this point the only power available on the PCI bus comes from an auxiliary power pin (A
14
.) If a PCI device has been enabled to wake up the machine it is allowed to draw up to 375 ma of current from the A
14
pin. If the PCI device is not enabled it can only draw a maximum of 20 ma.
So in a given PCI 2.2 compliant computer with multiple wake-up devices, if the operating system places the computer in the D
3
-cold power state, some devices will be allowed to wake-up the computer and correspondingly these same devices will be allowed to draw 375 ma of current from pin A
14
. Any device that is not enabled to wake up the computer can only draw 20 ma. The operating system must know the limitations of the power supply and not enable more devices than the power supply can handle.
In the D
3
-cold state, all PCI signals and power pins (except A
14
) are turned off, floating to ground (VSS). Since the reset pin on the PCI bus is active low, the power-management logic cannot be reset by this signal. If the power-management logic were reset by this signal it would be in a continual reset state during the D
3
-cold power state, and the logic would be unable to wake up the computer. This is the reason why the PME_Select bit, defined in the Power-Management Control Register is considered a “sticky bit.” This bit has no reset defined in the
PCI Bus Power Management Interface Specification
. The PME_Select bit, which enables the PCI device to wake up the PC, and enables it to draw power from pin A
14
, is considered to be in an indeterminate state at power-up of the auxiliary power line. Only once the operating system has loaded and has had a chance to write this bit is it properly specified.
By defining the PME_En bit as indeterminate at power-up the
PCI Power Management Interface Specification
avoids some types of ambiguity. Nevertheless this indeterminacy could cause system failures if the system cycles auxiliary power off and on in the D
3
-cold power state. In this case, the PME_En bit set by the operating system may be lost. Therefore, if auxiliary power cycles in a D
3
state many the devices on the PCI bus could take more power than the power-supply can handle in a D
3
-cold power state. This could result in the system not booting correctly or in extreme cases in the failure of source hardware in the PC.
Thus, client Wake-On-LAN devices or other power management clients, need to be properly configured to be able to wake-up the system. However, the configuration cannot be done reliably, when the system is susceptible to improper power down events, like the plug being accidently kicked out of the wall, a power blackout, or a power surge.
It is desirable to provide an apparatus that can properly initialize the wake-up functionality of a PCI device using only 20 ma of power, and which is extendable to a variety of bus systems and system components on the bus systems that monitor for power management events.
SUMMARY OF THE INVENTION
The present invention enables power management event monitoring in client components of a computer system, without requiring the client component to rely on the host operating system configured parameters to protect against overloading in the system power supply. This technique involves enabling the monitoring function in a low-power mode, and switching to an operating power mode only after the component is assured that it is validly configured to do so.
The low power event monitoring enabling of the present invention allows wake up devices to maintain their proper functionality in the event of a momentary power loss, or in the event the operating system does not properly load upon power-up. The invention is particularly suited for use with network interface card supporting Wake-On-LAN functions.
The present invention comprises a component for a system having power management resources that are responsive to power management event signals to switch to an operating state. Such systems in preferred embodiments include PCI bus systems with host computers and PCI client components coupled to the bus systems. The component according to the present mention comprises power logic having a first mode in which power consumption is limited to a first specified level and a second mode in which power consumption is limited to a second specified level higher than the first specified level. The compon

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