Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-01-28
2002-01-29
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S787000, C257S693000, C257S734000
Reexamination Certificate
active
06342730
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor chip packages, and more specifically to low-pin-count chip packages and manufacturing methods thereof.
2. Description of the Related Art
FIG. 1
is a low-pin-count chip package
100
according to a preferred embodiment disclosed in R. O. C. Publication No. 348306 entitled “Device Having Resin Package And Method Of Producing The Same” The low-pin-count chip package
100
includes a chip
110
sealed in a package body
120
. The active surface of the chip
110
is provided with a plurality of bonding pads
110
a
electrically connected to a plurality of connection pads
130
. The backside surface of the chip
110
is exposed from the package body
120
through a conductive adhesive layer
112
. The connection pads
130
are located at the periphery of the chip
110
and exposed from the lower surface of the package body
120
for making external electrical connection. Since the package body
120
does not cover the exposed lower surface of the connection pads
130
, it can not firmly lock the connection pads
130
.
The connection pads
130
are usually made of metal with good electrical conductivity such as copper but the package body
120
is made of insulating material such as epoxy molding compound. Accordingly, the bond between connection pads
130
and the package body
120
is relatively weak and the difference of the coefficient of thermal expansion (CTE) therebetween is very large. Because of the CTE mismatch, stresses are induced at the interface between the connection pads and the plastic package body as the conventional package experiences temperature cycling. The stresses, in turn, result in the delamination at the metal-plastic interface. When the delaminations had occurred at the plastic-metal interface, moistures from the environment are easy to penetrate into the plastic package body and accumulate in the delaminated area. Once moisture accumulates in the package, rapid temperature ramp-up will cause the moisture to vaporize and expand, thereby inducing an hygrothermal stresses in the delaminated area which causes the surrounding plastic package body to popcorn. One of the most common occurrence of package popcorning occurs when the package described above is surface-mounted to a printed wiring board during the InfraRed reflowing process.
Further, since the package body
120
only seals one side of the chip
110
, moisture and/or ionic contamination from the atmosphere can sometimes penetrate through the bonding lines between the epoxy molding compound and the chip
110
, which can cause reliability problems, i.e. a great reduction of the operating life of package. This phenomenon is becoming more and more critical as the semiconductor industry moves towards packaging electronic devices into a smaller and smaller packages.
SUMMARY OF THE INVENTION
The present invention therefore seeks to provide a low-pin-count chip package which overcomes, or at least reduces the above-mentioned problems of the prior art.
Accordingly, in a first aspect, the present invention provides a low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. A package body is formed over the semiconductor chip and the connection pads in a manner that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a substantially concave profile thereby enhancing the “locking” of the die pad and the connection pads in the package body as well as prolonging the path and time for moisture diffusion into the package
According to a second aspect, this invention further provides a method of producing a low-pin-count chip package. The method comprises the steps of: (A) providing a sheet carrier; (B) laminating a metal layer on the sheet carrier; (C) half-etching the metal layer so as to form concavities at predetermined regions thereof; (D) forming a photoresist layer on the metal layer; (E) half-removing the photoresist layer such that only photoresist within the concavities is left; (F) forming a metal coating on the surface of the metal layer which is not covered by the photoresist; (G) stripping the remaining photoresist within the concavities; (H) etching the metal layer so as to form a die pad and a plurality of connection pads having a substantially concave profile; (I) attaching a semiconductor chip onto the die pad; (J) electrically coupling the semiconductor chip to the connection pads; (K) forming a package body over the semiconductor chip and the connection pads wherein the substantially concave profile helps the package body to lock the connection pads in the package body; (L) removing the sheet carrier; and (M) forming a protective metal flash on the lower surfaces of pad and the connection pads.
REFERENCES:
patent: 5900676 (1999-05-01), Kweon et al.
patent: 6187614 (2001-02-01), Takata et al.
patent: 6198171 (2001-03-01), Huang et al.
patent: 6201292 (2001-03-01), Yagi et al.
patent: 6208023 (2001-03-01), Nakayama et al.
R.O.C. Publication No. 348306, dated Nov. 7, 1985, entitled Device Having Resin Package and Method of Producing the Same (English Abstract).
Jung Kyujin
Kang Kun-A
Park Hyung Jun
Advanced Semiconductor Engineering Inc.
Clark Jhihan B
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