Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
2001-09-28
2004-06-22
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S046000, C710S047000, C710S260000, C709S241000, C709S241000
Reexamination Certificate
active
06754738
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to communications between processes in a multiprocessor system, and more particularly relates to timing of initiative passing in an input/output (I/O) operation without interrupt overhead.
BACKGROUND OF THE INVENTION
U.S. Pat. No. 4,447,873 issued May 8, 1984 to Price et al. for INPUT-OUTPUT BUFFERS FOR A DIGITAL SIGNAL PROCESSING SYSTEM discloses buffer interfaces wherein a storage controller which generates control signals indicating when it is condition to receive a vector of data words from the storage controller, whereon the storage controller transfers a vector of data to the input buffer.
U.S. Pat. No. 5,671,365 issued Sep. 23, 1997 to Binford et al. for I/O SYSTEM FOR REDUCING MAIN PROCESSOR OVERHEAD IN INITIATING I/O REQUESTS AND SERVICING I/O COMPLETION EVENTS, and U.S. Pat. No. 5,875,343 issued Feb. 23, 1999 to Binford et al. for EMPLOYING REQUEST QUEUES AND COMPLETION QUEUES BETWEEN MAIN PROCESSORS AND I/O PROCESSORS WHEREIN A MAIN PROCESSOR IS INTERRUPTED WHEN A CERTAIN NUMBER OF COMPLETION MESSAGE ARE PRESENT IN ITS COMPLETION QUEUE disclose an apparatus wherein I/O requests are queued in a memory shared by one or more main processing units and one or more I/O processors. Each I/O processor is associated with a queue, and each main processing unit is associated with a queue shared with the I/O processors. Each I/O processor may continue processing queued I/O requests after completing processing an earlier request. A threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the main processing unit. Many events are batched together under one interruption.
U.S. Pat. No. 5,771,387 issued Jun. 23, 1998 to Young et al. for METHOD AND APPARATUS FOR INTERRUPTING A PROCESSOR BY A PCI PERIPHERAL ACROSS AN HIERARCHY OF PCI BUSES discloses a hierarchy of PCI buses for facilitating PCI agents coupled to the lower lever PCI buses to interrupt a processor during operation.
U.S. Pat. No. 6,032,217 issued Feb. 29, 2000 to Arnott for METHOD FOR RECONFIGURING CONTAINERS WITHOUT SHUTTING DOWN THE SYSTEM AND WITH MINIMAL INTERRUPTION TO ON-LINE PROCESSING discloses a method for concurrently reorganizing a disk file system while continuing to process I/O requests. The method includes stopping processing of new I/O requests by queuing them within the system, finishing processing I/O requests in progress, performing the reorganization, and then processing the queue of stored I/O requests before finally resuming normal operation.
U.S. Pat. No. 6,085,277 issued Jul. 4, 2000 to Nordstrom et al. for INTERRUPT AND MESSAGE BATCHING APPARATUS AND METHOD discloses an interrupt and batching apparatus for batching interrupt processing for many events together.
SUMMARY OF THE INVENTION
An apparatus, method and program product for sending data to or receiving data from one or more I/O devices in an I/O operation with a main storage controlled by a processor in a data processing system. The apparatus includes a time-of-day (TOD) register for containing a TOD value, a clock for containing a current TOD value, and a summary register having a first condition when any one of said devices requests an I/O operation and a second condition when no devices have an outstanding I/O request, each device having an outstanding I/O request sets the summary register to its first condition only when the summary register is in its second condition, and further places the current TOD value in the TOD register. A checking program determines if a specified time delay has been exceeded between the value in said TOD register and the current TOD for each requested I/O operation. The checking program drives an interrupt to the processor when the specified time delay has been exceeded
The present invention provides for the direct cooperation between devices and the Operating System (OS) of a host computer. This cooperation is implemented by the OS informing devices of a target delay interval that, when exceeded, requires the device to drive a low overhead I/O interrupt. If a device detects that at least one other device has status pending in the completion vectors for longer than the specified amount of time, then the device should drive an interrupt. As with any interrupt model, driving an interrupt may not improve the application perceived response time, depending upon the application's dispatching priorities. If a device detects that the OS specified target interval has not yet been exceeded, then setting of disclosed completion vector bytes is all that is required (i.e. it is anticipated that dispatcher polling will process the I/O completion without requiring an interrupt).
It is another object of the present invention to provide a method and apparatus which, when the dispatcher polling on the target OS image is responsive to incoming I/O completions, the overhead incurred by processing I/O interrupts can be avoided.
It is another object of the present invention to provide a method and apparatus which, when polling is not responsive, very low cost I/O interrupts are driven. These interrupts are low cost because all they do is cause the processor to poll the completion vectors. No detailed information is queued as to which device requires attention, therefore the amount of serialization/complexity required to drive the interrupt is significantly reduced.
It is another object of the present invention to provide a method and apparatus which provides for interrupts from multiple sources which are coalesced into a single notification event. This allows even the low cost interrupt to be amortized across multiple device completions.
REFERENCES:
patent: 3789365 (1974-01-01), Jen et al.
patent: 4024505 (1977-05-01), Sperling
patent: 4220990 (1980-09-01), Alles
patent: 4447873 (1984-05-01), Price et al.
patent: 4638424 (1987-01-01), Beglin et al.
patent: 5506987 (1996-04-01), Abramson et al.
patent: 5581770 (1996-12-01), Suzuki
patent: 5671365 (1997-09-01), Binford et al.
patent: 5708814 (1998-01-01), Short et al.
patent: 5875343 (1999-02-01), Binford et al.
patent: 5881296 (1999-03-01), Williams et al.
patent: 6032217 (2000-02-01), Arnott
patent: 6085277 (2000-07-01), Nordstrom et al.
patent: 6549981 (2003-04-01), McDonald et al.
Brice, Jr. Frank W.
Easton Janet R.
Glassen Steven G.
Oakes Kenneth J.
Schmidt Donald W.
Gonzalez Floyd A.
International Business Machines - Corporation
Perveen Rehana
LandOfFree
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