Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-22
2003-03-25
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S337000, C257S378000
Reexamination Certificate
active
06538281
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and in particular to an LDMOS structure whose enhanced characteristics make it capable of withstanding high currents while retaining a low on-resistance.
BACKGROUND OF THE INVENTION
A laterally diffused metal oxide semiconductor (LDMOS) structure is formed by a drain region, a source region and a gate defined over a channel region. Most commonly, the source region is formed by a P-body diffusion formed inside an N-pocket region. A N+ source diffusion is formed inside the P-body, and a source contact is established with the N+ diffusion. This type of structure has a number of drawbacks because during the normal functioning of the device, the potential of the N+ diffusion normally differs from the potential of the body diffusion.
In order to improve the performance of a power LDMOS, particularly when operating at relatively high currents, the N+ and P-body diffusions should be short-circuited locally. According to
FIG. 1
, this may be attained by forming an electrical connection by way of a P+ diffusion that extends through the N+ source diffusion and reaches the P-body region that is short-circuited to the N+ diffusion by the source contact.
Such a locally established short-circuit between the N+ and P-body diffusions is a customary technique implemented in VSLI technology where the size of the contacts are large enough to establish the desired contact with both the P+ and N+ diffusions.
With the development of ULSI technologies, the size of the contacts have been reduced to allow for a greater density of integration, and as a result, the N+ and P+ diffusions may hardly be short-circuited by a single contact.
As a result, known ULSI LDMOS structures encompass source regions with contacts on the N+ diffusions and contacts on the P+ diffusions, as shown in FIG.
2
. As illustrated, the central contact of the source region is almost exclusively formed on the P+ diffusion, whereas the other two source contacts are formed on the N+ diffusion. The local short-circuit between the P+ and N+ diffusions is therefore established through a common source contact metallization.
Such an approach has the drawback of causing the current to be nonuniform in the source region because, as shown in
FIG. 3
, the charge carriers are collected through distinct contacts. This reduces the robustness of the device when operating at high currents because of a premature turning on of the intrinsic parasite NPN.
Moreover, the layout of the contacts in the source region, which in known LDMOS structures are generally aligned as shown in
FIG. 2
, influences the value of the on-resistance.
In a scheme like this, the on-resistance is proportional to the pitch between the source contacts and the drain contacts, and inversely proportional to the width W of the drain and source regions. Once the width W of the drain and the source regions are fixed, the on-resistance may be lowered only by reducing as much as possible the distance between such regions within the limits imposed by the fabrication technology.
SUMMARY OF THE INVENTION
Eliminating the source contacts on the N+ diffusions while establishing the necessary local short-circuit between the N+ and P+ diffusions reduces the width of the source region with respect to the eliminated contacts.
Moreover, by eliminating the drain contacts that are commonly formed directly opposite the source contacts on the P+ regions, the distance between the drain regions and the source regions may be further narrowed, thus obtaining an LDMOS structure with a lower on-resistance. In addition, by locally establishing the required short-circuit, a net improvement in terms of current uniformity is achieved because there are only common contacts rather than any separate contacts on the N+ and P+ diffusions.
The present invention achieves all this and effectively overcomes the problem of the current being nonuniform in the source region while providing for a markedly lower on-resistance as compared to known LDMOS structures.
More specifically, the object of the present invention is to provide an LDMOS structure formed in a region of a first type of conductivity of a semiconductor substrate. The LDMOS structure comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity formed inside the first region, and a source diffusion of the first type of conductivity formed inside the body diffusion. A diffusion of a second type of conductivity is in a limited area of the source region, which functions as an electrical connection that extends through the layer of the source diffusion and reaches the body region. At least one source contact is established with the source diffusion and with the electrical connection diffusion.
According to an essential aspect of the LDMOS structure of the invention, a layer of silicide present over the whole source region area short-circuits the source diffusion and the electrical connection diffusion while the source contact is established with the silicide layer.
According to a preferred embodiment of the invention, the source contact is projectively formed over the area of the electrical connection diffusion. Of course, the LDMOS structure of the invention may comprise a number of uniformly spaced drain contacts on respective drain regions, and a number of uniformly spaced source contacts on respective source regions, alternated in the overall layout of the structure with drain regions.
Optionally, the source contacts may not be aligned with the drain contacts on the adjacent drain regions, and the source regions and the drain regions may be advantageously widened with respect to the respective contacts. In this case, the gates will be geometrically defined along the wavy boundaries of the source regions widened with respect to the source contacts.
REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 4672410 (1987-06-01), Miura et al.
patent: 4683486 (1987-07-01), Chatterejee
patent: 4866492 (1989-09-01), Quigg
patent: 4873560 (1989-10-01), Sunami et al.
patent: 4943841 (1990-07-01), Yahara
patent: 4969032 (1990-11-01), Scheitlin et al.
patent: 5308782 (1994-05-01), Mazure et al.
patent: 5317180 (1994-05-01), Hutter et al.
patent: 5369045 (1994-11-01), Ng et al.
patent: 5517046 (1996-05-01), Hsing et al.
patent: 5825065 (1998-10-01), Corsi et al.
patent: 6144065 (2000-11-01), Kinzer
patent: 6169309 (2001-01-01), Teggatz et al.
patent: 1184800 (1965-01-01), None
patent: 0537684 (1993-04-01), None
patent: 47-39134 (1968-04-01), None
(no author), Recent Developments at the National Bureau of Standards . . . , p. 85 & 138-141, Nov. 1953, Tele-Tech & Electronic Industries.
Shah et al, A 4-Mbit DRAM with Trench-Transistor Cell, p. 618-626, Oct. 1986, IEEE Journal of Solid State Circuits.
Banerjee et al, Leakage Mechanisms in the Trench Transistor DRAM Cell, p. 108-116, Jan. 1988, IEEE Transactions on Electron Devices.
Richard C. Jaeger, Introduction to Microelectronic Fabrication, p. 136-138, Feb. 1990, Modular Series on Solid State Devices (vol. 5).
Croce Giuseppe
Galbiati Paola
Merlini Alessandra
Moscatelli Alessandro
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Nelms David
Nguyen Dao H.
STMicroelectronics S.r.l.
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