Low noise tri-state output buffer

Details Low noise tri-state output buffer Low noise tri-state output buffer

1995-07-14

1996-10-22

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 87, 326 58, H03K 1716

Patent

active

055680623

ABSTRACT:
A buffer circuit includes a pair of pull-up output transistors and a pair of pull-down output transistors driving an output line. Each output transistor is driven by its own tristate input translator, all connected to an input terminal of the circuit. Two of the translators are tristated by control signals received as feedback from the output line to turn off one of the pull-up transistors when the output exceeds the high logic level transition voltage (2.2 V) and to turn off one of the pull-down transistors when the output drops below the low logic level transition voltage (0.8 V). This not only prevents ground bounce or overshoot of the output, but also avoids larger current flow or power dissipation from pull-up and pull-down transistors being simultaneously partially on during a transition. Because the output transistors are driven directly by the input translators, throughput speed is improved, while ramp rate of the translator outputs driving the output transistors can remain slow to reject input noise spikes and avoid generation of output noise.

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