Low noise, reduced swing differential output buffer design

Details Low noise, reduced swing differential output buffer design Low noise, reduced swing differential output buffer design

2000-12-20

2003-03-04

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C327S083000, C327S378000

Reexamination Certificate

active

06529036

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing buffers generally and, more particularly, to a method and/or architecture for implementing differential, reduced swing buffers.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a conventional reduced swing buffer
10
is shown. Reduced swing buffers are typically implemented in serial data communication and high speed data transfer applications. The buffer
10
implements current steering utilizing a scaled replica biasing scheme. The conventional reduced swing buffer
10
comprises a negative bias circuit
12
and a driver circuit
14
. The bias circuit
12
implements a resistor R
1
and a resistor R
2
. The driver circuit
14
implements a resistor R
3
, a resistor R
4
and a resistor R
5
. The resistors R
1
, R
2
, R
3
, R
4
and R
5
are external resistors. The external resistors R
1
, R
2
, R
3
, R
4
and R
5
require the circuit
10
to implement additional external components. The resistors R
1
-R
5
are required since a customer needs to configure (i.e., add) a proper resistance to the circuit
10
. The circuit
10
is resistance matched at a load end and not at the source end. The bias circuit
12
implements a minimum negative bias transistor MNBIAS
1
in a saturated region. The driver circuit
14
implements a minimum negative bias transistor MNBIAS
2
in a saturation region. The saturated transistors MNBIAS
1
and MNBIAS
2
require additional pins to receive the negative bias signal NBIAS. Additionally, the driver circuit
14
cannot implement a resistor across a true output (i.e., OUT) and a complement output (i.e., OUTb).
SUMMARY OF THE INVENTION
The present invention concerns a circuit configured to match an impedance of a first pin and a second pin coupled to a transmission line. A first resistor is generally coupled to the first pin and a second resistor is generally coupled to the second pin. The first and second resistors may be coupled to a common node to provide an output voltage level independent of process corner and temperature variation.
The objects, features and advantages of the present invention include providing a method and/or architecture for a differential reduced swing buffer that may (i) allow high and low output levels to remain constant across process corner and temperature, (ii) represent matched impedance of a transmission line, (iii) have an output swing less sensitive to variation in a particular load resistor value, (iv) not require any external pins to implement a replica circuit, and/or (v) have less switching noise (Ldi/dt) because of current steering.


REFERENCES:
patent: 5374861 (1994-12-01), Kubista
patent: 5519353 (1996-05-01), Rainal
patent: 6025742 (2000-02-01), Chan
patent: 6204692 (2001-03-01), Nakagawa
patent: 6414512 (2002-07-01), Moyer
patent: 404108216 (1992-04-01), None
“Gigabit-per-Second, ECL-Compatible I/O Interface in 0.35-&mgr;m CMOS”, By Hormoz Djahanshahi et al., IEEE Journal of Solid State Circuits, vol. 34, No. 8, Aug. 1999, pp. 1074-1083.

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