Low noise output buffer circuit

Details Low noise output buffer circuit Low noise output buffer circuit

1996-02-21

1997-09-30

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 86, H03K 1716

Patent

active

056729839

ABSTRACT:
An output buffer circuit is provided with at least two output MOS transistors of the same type. Each of the two output MOS transistors has a source terminal connected to a power supply or a ground and further has drain terminals connected to an output pad. Resistive elements connect the gate terminals of these output MOS transistors. An input terminal of an inverter is connected to an input signal line and an output terminal of the inverter is connected to the gate terminal of a first one of the at least two output MOS transistors. A charging MOS transistor of the same type as the at least two output MOS transistors has a drain terminal connected to the gate terminal of a second one of the at least two output MOS transistors. The charging MOS transistor has a source terminal connected to either the power supply or the ground and has a gate terminal connected to the input signal line.

REFERENCES:
patent: 5089722 (1992-02-01), Amedeo
patent: 5124579 (1992-06-01), Naghshineh
patent: 5140194 (1992-08-01), Okitaka
patent: 5194764 (1993-03-01), Yano et al.
patent: 5231311 (1993-07-01), Ferry et al.
patent: 5315172 (1994-05-01), Reddy
patent: 5517129 (1996-05-01), Matsui

Affiliated with

Also associated with

Rating

Low noise output buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low noise output buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low noise output buffer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2259722