Low noise logic family

Details Low noise logic family Low noise logic family

1994-08-18

1996-05-07

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 30, 326115, 326119, H03K 1908, H03K 19003

Patent

active

055149820

ABSTRACT:
A low noise logic (LNL) family is disclosed. An inverter 10 has a pair of load devices NL1, NL2 coupled to the drains of NMOS transistors N 1, N2. The input signal is coupled to the gate of N 1. The drain of N 1 is coupled to the gate of N2. A constant current source 12 is coupled between V.sub.ss and the sources of the transistors N1,N2. Trickle current devices NTR1, NTR2 are coupled to the drains of N 1, N2, respectively to insure input control of the output states. A high logic signal on the gate of N1 steers the constant current to the load NL1 and turns NL2 off. A low logic signal on the gate of N1 turns N1 off and applies a high voltage to the gate of N2, turning N2 on. N2 steers the constant current to NL2.

REFERENCES:
patent: 3700981 (1972-10-01), Masuhara et al.
patent: 3917958 (1975-11-01), Hatsukano
patent: 4661725 (1987-04-01), Chantepie
patent: 4885479 (1989-12-01), Oritani
patent: 4924116 (1990-05-01), Vu et al.
P. R. Gray & R. G. Meyer, "Analog Integrated Circuits", 2nd Ed., John Wiley & Sons, pp. 61-70, 1984, New York.
Allstot et al., "Analog Logic Techniques Steer Around The Noise", IEEE Journal of Circuits & Devices, pp. 18-21, 1993.
D. J. Allstot, S. Kiaei, & R. H. Zele, "Analog Logic Techniques Steer Around the Noise", IEEE Journal of Circuits & Devices, pp. 18-21, 1993.

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