Low-noise leakage-tolerant register file technique

Details Low-noise leakage-tolerant register file technique Low-noise leakage-tolerant register file technique

2007-01-09

2007-01-09

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189030

Reexamination Certificate

active

10879090

ABSTRACT:
A memory circuit includes a word line, a data storage circuit including one or more memory cells or sub-cells, and an inverter coupled between the word line and the N memory cells. The inverter inverts a word-line signal input into a read port of the cells or sub-cells. Because the word-line inverter is local to each cell or sub-cell, DC offset is substantially reduced which translates into a reduction in leakage current.

REFERENCES:
patent: 5502683 (1996-03-01), Marchioro
patent: 5590087 (1996-12-01), Chung et al.
patent: 5618473 (1997-04-01), Sauter et al.
patent: 5886942 (1999-03-01), Akita
patent: 5951702 (1999-09-01), Lim et al.
patent: RE36404 (1999-11-01), Kameda et al.
patent: 6011746 (2000-01-01), Oh
patent: 6088267 (2000-07-01), Atsumi et al.
patent: 6885595 (2005-04-01), Sumita
patent: 2004/0139271 (2004-07-01), Khellah et al.

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