Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent
1996-07-16
1997-08-12
Hudspeth, David R.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
326 27, 326 82, H03K 19003
Patent
active
056569475
ABSTRACT:
A digital output buffer uses an RC delay line having more than one resistor and capacitor as a shaping circuit which drives an operational amplifier configured as voltage follower that drives an output load through a bond wire according to an embodiment, thereby achieving low ground and power supply bounce and nearly constant propagation delay under all process, temperature, and capacitive load variations. In another embodiment, taps from an RC delay line are used to drive a distributed MOS source follower. In yet another embodiment, taps from the RC delay line are used to drive the distributed MOS source follower while the final tap drives a rail-to-rail operational amplifier configured as a voltage follower. In that embodiment, the operational amplifier includes a fully complementary adaptive biasing structure which allows large overdrive voltages for the output devices. Most of the load current is supplied by the distributed MOS source follower, so that the operational amplifier must only correct the output signal shape and drive the output to the relevant power supply voltage after the distributed MOS source follower cuts off one threshold voltage short of the final output voltage. In yet another embodiment, the digital output buffer having an RC delay line, a distributed MOS source follower, and an operational amplifier is a tri-state output buffer. In that embodiment, the operational amplifier output drivers are disabled and the power supplies are disconnected from the RC delay line and the distributed MOS source follower when the output buffer is disabled.
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Hudspeth David R.
National Semiconductor Corporation
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