Low-noise cryogenic MOSFET

Details Low-noise cryogenic MOSFET Low-noise cryogenic MOSFET

1992-07-24

1994-10-18

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257607, 257610, 257612, H01L 2701, H01L 29167

Patent

active

053571304

ABSTRACT:
A microelectronic device of the MOSFET type (20) is structured to exhibit low noise characteristics at cryogenic temperatures of less than about 40K. The device (20) comprises a doped silicon substrate wafer (22), the dopant having an ionization energy in the substrate of more than about 0.1 eV. Preferred substrate dopants include tellurium as an n-type dopant and indium as a p-type dopant. A metal-oxide-semiconductor field effect transistor (20) in the substrate wafer (22) includes a source (24), a drain ( 26 ), and a gate (30) intermediate the source (24) and the drain (26).

REFERENCES:
Stuart Tewksbury et al., "Strong Carier Freezeout Above 77K in Tellurium-Doped Buried-Channel MOS Transistors," IEEE Trans. on Electron Devices, vol. ED-32, No. 1, pp. 67-69 (1985).
F. Scholz et al., "Low Frequency Noise and DLTS As Semiconductor Device Characterization Tools," Solid State Electronics, vol. 31, No. 2, pp. 205-217 (1988).
F. Scholz et al., "Low Frequency Noise as a Process Development and Characterization Tool," Electrochemical Society Proc., pp. 240-263 (1988).
David C. Murray et al., "Shallow Defects Responsible for GR Noise in MOSFET's," IEEE Trans. on Electron Devices, vol. 38, No. 2, pp. 407-416 (Feb. 1991).

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