Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Bidirectional rectifier with control electrode
Reexamination Certificate
1998-12-03
2001-01-30
Tran, Minh Loan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Bidirectional rectifier with control electrode
C257S119000, C257S109000, C257S112000, C257S126000, C257S772000, C257S773000, C257S784000
Reexamination Certificate
active
06180964
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to bond pads formed on semiconductor devices, and deals more particularly with a bond pad structure which prevents leakage current between adjacent bond pads, as well as to a method of making such structures.
BACKGROUND OF THE INVENTION
As part of the process for fabricating semiconductor devices, an integrated circuit chip is frequently assembled in a package in a final process step to complete the fabrication process. The assembled package can then be connected to a printed circuit board as part of a larger circuit to establish an electrical connection between the integrated circuit chip and the board. A wire bonding process is frequently used to connect the multiplicity of bond pads formed on the integrated circuit to the outside, or surrounding circuitry.
In a typical integrated circuit chip, active circuit elements such as transistors, resistors, capacitors, etc., are positioned in the central portion, i.e., the active region of the chip while the bond pads are normally arranged around the periphery of the active region, so that the active circuit elements are not likely to be damaged during a subsequent bonding process. When a wire bonding process is performed on a bond pad formed on an IC chip, the process normally entails the bonding of a gold or aluminum wire to the bond pad by fusing the two together with ultrasonic energy. The wire is then pulled so as to stretch the wire away from the bond pad after the bond between the wire and the pad is formed.
As the complexity and density of IC chips continues to increase, the number of adjacent bond pads and their proximity to each other increases. Because the bond pads are normally formed on a common semiconductor substrate, electrical current sometimes leaks between adjacent bond pads through the substrate, thus giving rise to reduced signal level, signal errors, or even short circuits producing circuit malfunction.
Accordingly, there is a clear need in the art for an improved bond pad structure that exhibits improved electrical isolation between adjacent bond pads, thereby preventing leakage currents between the pads. The present invention is directed to satisfying this need in the art.
SUMMARY OF THE INVENTION
According to one aspect of the invention, an improved bond pad structure for semiconductor devices is provided which exhibits increased electrical isolation between adjacent pads and prevents current leakages between the pads which contributes to device malfunction. The bond pad structure comprises a well of P+ or N+ types of semiconductor material formed in a semiconductor substrate of a P+ or N+ type material opposite that of the well. A region of P+ or N+ type material identical to that of the substrate is formed within the well and includes an exposed surface onto which a bonding pad is formed. P+ or N+ type materials are chosen for the substrate, well and regions within the well so as to form two pn interfaces through current must flow between the bond pad and the substrate. These two pn interfaces or junctions provide the electrical equivalent of two diodes connected in series and arranged in opposite polarity so as to provide isolation, regardless of whether a positive or negative voltage is applied to the bond pad.
According to another aspect of the invention, a semiconductor bond pad structure is provided comprising a semiconductor substrate of one of a P+ or N+ material, and a plurality of first regions defined in the substrate and formed of a semiconductor material of the other of P+ or N+ type materials, the interface between each of the first regions in a substrate defining a first pn junction. A plurality of second regions are respectively formed within the first regions and include the same P+ or N+ type materials selected for the substrate; the interface between each of the first and second regions define a second pn junction. A plurality of bonding pads are respectively formed on the surface of the second regions, whereby electrical current passing through the bonds and the substrate flows through the respectively associated first and second regions. The first and second pn regions provide the electrical equivalent of a pair of reverse connected diodes that provide electrical isolation preventing leakage current between adjacent ones to the bonding pads.
According to another aspect of the invention, a method is provided for forming a semiconductor bond pad structure, which comprises the steps of. (A) providing a semiconductor substrate of one of a P+ or P− type material; (B) forming a plurality of first regions within the substrate of the other of the P+ or P− type materials; (C) forming a plurality of second regions respectively within the first regions, the second regions being of the same P+ or P− type of materials as the substrate; and, (D) forming a plurality of bonding pads respectively on the surface of the second regions, the first and second regions providing electrical isolation preventing leakage current between adjacent ones on the bonding pad.
Accordingly, it is a primary object of the present invention to provide a bonding pad structure for semiconductor devices which substantially reduces or eliminates leakage currents through the bond pads and thus exhibits better electrical isolation between adjacent bond pads.
Another object of the present invention is to provide a bond pad structure as describe above which may be easily and reliably manufactured using common semiconductor processing techniques.
Another object of the present invention is to provide a bond pad structure as described above which achieves electrical isolation between adjacent bond pads for the application of both positive and negative voltages to the pads.
A still further object of the present invention is to provide a method of forming a bond pad structure which includes a minimum of conventional, reliable processing steps.
These, and further objects and advantages of the present invention will be made clear or will become apparent during the course of the following description of a preferred embodiment of the invention.
REFERENCES:
patent: 4967243 (1990-10-01), Baliga et al.
Cheng T.
Wu Lin-June
Yiu Ho-Yin
Taiwan Semiconductor Manufacturing Co. Ltd
Thai Luan
Tran Minh Loan
Tung & Associates
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