Low leakage substrate plate DRAM cell

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257301, 257305, H01L 2968, H01L 2978, H01L 2992

Patent

active

053008006

ABSTRACT:
Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor disposed in a trench formed in a semiconductor substrate and an access transistor disposed in a well which is opposite in conductivity type to that of the substrate and a buried oxide collar which surrounds an upper portion of the trench.

REFERENCES:
patent: 4523213 (1985-06-01), Konaka et al.
patent: 4688063 (1987-08-01), Lu et al.
patent: 4792834 (1988-12-01), Uchida
patent: 4849371 (1989-07-01), Hansen et al.
patent: 4967248 (1990-10-01), Shimizu
Davari, B., et al., "A Variable-Size Shallow Trench Isolation (STI) Technology with Diffused Sidewall Doping for Submicron CMOS", IEDM Tehcnical Digest, 92 (1988).
Bronner, G. B., et al., "Epitaxy Over Trench Technology for ULSI DRAMs", 1988 Symposium on VLSI Technology, p. 21 (May 10-13, 1988).
Cottrell, P., et al., "N-Well Design for Trench DRAM Arrays", IEDM Technical Digest, 584 (1988).
Nobel, W. P., et al., "Parasitic Leakage in DRAM Trench Storage Capacitor Vertical Gated Diodes", IEDM Technical Digest, 340 (1987).
Lu, N., et al., "The SPT Cell-A New Substrate-Plate Trench Cell for DRAMs", IEDM Technical Digest, 771 (1985).

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