Low leakage SRAM scheme

Details Low leakage SRAM scheme Low leakage SRAM scheme

2006-05-02

2006-05-02

Lee, Thomas C. (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S323000, C713S324000

Reexamination Certificate

active

07039818

ABSTRACT:
A memory device (20) having substantially reduced leakage current in a sleep/data retention mode whereby at least a portion (25, 28) of the periphery circuitry (24) shares the same power supplies VDDA and/or VSSA of the memory array (22) such that during sleep/data retention mode the voltage across both the portion (25, 28) of the periphery circuitry (24) and the memory array (22) of the selected SRAM block is reduced, while all other circuits can be shut down except the sleep control circuits as well as selected latches, flip-flops, etc. whose contents need to be retained. A sequence for powering up and shutting down portions of the periphery circuitry (24) and the external circuitry (26) is also provided.

REFERENCES:
patent: 5590082 (1996-12-01), Abe
patent: 5740118 (1998-04-01), Sato et al.
patent: 6256252 (2001-07-01), Arimoto
patent: 6414894 (2002-07-01), Ooishi et al.
patent: 6657911 (2003-12-01), Yamaoka et al.
patent: 6678202 (2004-01-01), Scott
patent: 6768144 (2004-07-01), Houston et al.

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