Low leakage ROM architecture

Details Low leakage ROM architecture Low leakage ROM architecture

2008-12-31

2011-10-04

Lappas, Jason (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S185210, C365S205000, C365S207000

Reexamination Certificate

active

08031541

ABSTRACT:
Read only memory (ROM) with minimum leakage is provided. The ROM includes a read only memory array. The read only memory array includes a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. Another ROM includes a first transistor comprising a gate, electrically connected to a word line to provide a read signal, a drain, electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal. Further, a reference word line is electrically connected to a gate of a fourth transistor.

REFERENCES:
patent: 2003/0189851 (2003-10-01), Brandenberger et al.

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