Low leakage one transistor static random access memory

Details Low leakage one transistor static random access memory Low leakage one transistor static random access memory

2006-06-20

2006-06-20

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

07064371

ABSTRACT:
The invention forms a 1T Static Random Access Memory (SRAM) with a low concentration cell node region and a higher concentration bit line region (e.g., second bit line region). The method of the invention forms a 1T Static Random Access Memory (SRAM) that uses a resist mask to block a high concentration implant into the cell node region, but allows the high concentration implant into the bit line region to form a second (high concentration) bit line. The invention's 1T SRAM, with the low concentration cell node, has reduced p-n junction leakage at the cell node and increase date retention time.

REFERENCES:
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5686336 (1997-11-01), Lee
patent: 5953606 (1999-09-01), Huang et al.
patent: 5998820 (1999-12-01), Chi
patent: 6078087 (2000-06-01), Huang et al.
patent: 6262447 (2001-07-01), Chi
patent: 6274441 (2001-08-01), Mandelman et al.
patent: 6504780 (2003-01-01), Leung
Leung et al., “The Ideal SoC Memory: 1T-SRAM”, 13th International ASIC/SoC Conference Proceedings, IEEE, Sep. 13-16, 2000, pp. 32-35.

Affiliated with

Also associated with

Rating

Low leakage one transistor static random access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low leakage one transistor static random access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low leakage one transistor static random access memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3677131