Low-leakage MOS planar capacitors for use within DRAM...

Details Low-leakage MOS planar capacitors for use within DRAM... Low-leakage MOS planar capacitors for use within DRAM...

2000-10-17

2002-07-16

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S145000

Reexamination Certificate

active

06421269

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to semiconductor storage devices and, more particularly, to capacitor structures for use therein.
BACKGROUND OF THE INVENTION
Dynamic random access memories (DRAM) are the semiconductor storage devices of choice for maximizing the number of data bits stored per unit surface area on a chip. A typical 1T DRAM cell includes only a single MOS access transistor and a corresponding storage capacitor. In contrast, a static RAM cell includes between 4 and 6 MOS devices. During DRAM cell operation, the storage capacitor holds one level of charge to represent a “logic one” and another level of charge to represent a “logic zero.” The access transistor is used to controllably couple the storage capacitor to a bit line during read and/or write operations.
It is often desirable to embed DRAM storage devices within logic circuitry to provide high-density, on-chip storage capabilities for the logic circuitry. To embed such devices without requiring a change in the logic process, chip manufacturers commonly utilize the gate oxide layer of the logic transistors to provide the storage capacitors of the DRAM cells. The need for improving the performance of the logic transistors, however, has lead to a steady reduction in the thickness of the gate oxide layer used in logic circuits. Although this reduction in thickness provides an increased capacitance per unit surface area, it also results in an increase in gate-oxide leakage. Therefore, storage capacitors making use of these oxide layers typically display a decreased charge retention time, which is undesirable in a memory chip.
Therefore, there is a need for a method and apparatus for increasing the charge retention time of a DRAM storage capacitor having a relatively thin oxide layer.


REFERENCES:
patent: 5400275 (1995-03-01), Abe et al.
Itoh, K., “Trends in Megabit DRAM Circuit Design”,IEEE Journal of Solid-State Circuits, 25 (3), pp. 778-789, (Jun. 1990).

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