Low leakage monotonic CMOS logic

Details Low leakage monotonic CMOS logic Low leakage monotonic CMOS logic

2006-08-01

2006-08-01

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S095000, C326S098000

Reexamination Certificate

active

07084667

ABSTRACT:
A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.

REFERENCES:
patent: 6040707 (2000-03-01), Young et al.
patent: 6249145 (2001-06-01), Tanaka et al.
patent: 6635934 (2003-10-01), Hidaka
patent: 2002/0008999 (2002-01-01), Hidaka

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