Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-06-26
2002-10-15
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S514000, C438S528000, C438S787000, C438S918000
Reexamination Certificate
active
06465370
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to semiconductors and more particularly to material used in semiconductors to provide low capacitance dielectric isolation.
As is known in the art, semiconductors devices have a wide range of applications. Many of these applications require the use of a dielectric to provide isolation between active devices, between conductive plates of a capacitors of the type used in dynamic random access memories (DRAMs), and between layers of conductive material, for example. Typical isolation materials are silicon dioxide and silicon nitride. Silicon dioxide is typically used to electrically isolate devices, for example. In order to obtain a relatively high capacitance with a relatively thin layer of dielectric material, silicon nitrite is typically used because it has a higher dielectric constant that silicon dioxide. For example, in a trench capacitor used in some DRAMs, a trench is formed in a silicon substrate, the walls of the trench are then exposed to hydrogen to pre-clean or smooth the walls of the trench and to thereby obtain a uniformly deposited (e.g. thermal and LPCVD deposited) silicon nitride layer over the pre-cleaned trench walls. The hydrogen pre-clean is typically performed at a temperature of 700° C. to 950° C. and a pressure of 100 Torr for a single wafer Rapid Thermal Chemical Vapor Deposition (RTCVT) or 1-20 Torr for batch furnaces. It is noted that one or two mono-layers of native silicon dioxide (i.e., silicon dioxide layers below one nanometer thickness formed because of clean room oxygen which are typically present) may be formed over the silicon walls of the trench prior to the deposition of the silicon nitride layer. During the hydrogen pre-cleaning step, the thickness of any native silicon dioxide may be reduced thereby enabling the formation of a more nitrogen rich layer to thereby increase the capacitance of the trench capacitor. As noted above, silicon dioxide is used as an isolation material having thickness of at least 2-5 nanometers for gate oxides; however, the use of a hydrogen pre-clean is not used because this would degrade implanted device regions by interaction of hydrogen with dopants such as arsenic, phosphorous and boron.
SUMMARY OF THE INVENTION
In accordance with one feature of the invention, a method is Provided for reducing the capacitance of a capacitor formed on a silicon substrate. The capacitor has, as a dielectric thereof, a silicon dioxide layer on a surface of the silicon substrate. The method includes the step introducing hydrogen atoms into a portion of said surface to decrease the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric and hence reducing the capacitance of said capacitor.
In accordance with another feature of the invention, the method including the step of forming the silicon dioxide layer with a thickness greater than two nanometers.
In accordance with another feature of the invention, the step of introducing hydrogen comprises baking in hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr.
In accordance with another feature of the invention, the step of introducing hydrogen comprises the step of forming hydrogen atoms in the surface with concentrations of 10
17
atoms per cubic centimeter, or greater.
In accordance with still another feature of the invention, a DRAM cell is provided having a transistor coupled to a capacitor. The cell includes a silicon substrate having the transistor and the capacitor disposed in the substrate. The transistor has source and drain regions having a first type conductivity disposed in an upper portion of the substrate. The source and drain regions are disposed in a well in the substrate. The well has a conductivity type opposite to the first type conductivity. The capacitor is a trench capacitor and includes a first dielectric layer disposed on intermediate and lower walls of the trench. A first conductive material is disposed in the trench on the first dielectric layer and an upper portion of such first conductive material. The first conductive material is electrically connected to one of the source and drain regions through a node region disposed in the substrate between such one of the source and drain regions and the upper portion of the first conductive material in the trench. The first conductive material provides a first electrode for the capacitor. A second conductive material is disposed in the substrate about the lower portion of the trench. The second conductive material has the first type conductivity and is dielectrically separated from the first conductive material by the lower portion of the first dielectric material to provide a second electrode for the capacitor. A second dielectric material is disposed the substrate about the intermediate portion of the first dielectric region to dielectrically isolate the node region of the trench from the second conductive material. A hydrogen passivation layer is disposed in the intermediate portion of the substrate about portions of the second dielectric material.
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J.M.Green et al.; “Silicon Wafers With High-Dielectric Integrity”; IBM Technical Disclosure Bulletin; vol. 16, No. 6; Nov. 1973.
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Hoepfner Joachim
Schrems Martin
Vollertsen Rolf-Peter
Braden Stanton
Infineon - Technologies AG
Lee Eddie
Richards N. Drew
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