Low leakage logic gates

Details Low leakage logic gates Low leakage logic gates

2001-10-17

2002-07-23

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S027000, C326S087000, C326S121000

Reexamination Certificate

active

06424174

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of CMOS (complimentary-metal-oxidesilicon) integrated circuits; more specifically, it relates to a CMOS circuit design with increased tolerance to quantum mechanical tunneling or other gate leakage.
2. Background of the Invention
The shrinking of MOSFETs (metal-oxide-silicon-field-effect-transistor) in integrated circuits is based upon the concept of scaling. That is a large FET is scaled to produce a smaller FET with similar behavior. According to the scaling concept, decreasing the voltages and dimensions of an FET by 1/k and increasing the doping and charge densities by k will result in the electric field configuration inside the scaled FET remaining the same as in the unscaled FET. The result is in an increase in FET speed and a decrease by 1/k
2
in power consumption, among other effects.
However, one serious limitation to the scaling model is quantum mechanical tunneling of electrons through very thin gate dielectrics. As the gate dielectric is made thinner the gate capacitance increases according to equation (1):
C=
e/t
ox
  (1)
where C is the gate capacitance per unit area, e is the dielectric constant of the gate dielectric and t
ox
is the thickness of the gate dielectric. This results in a total charge stored across the gate according to equation (2):
Q=CV
where Q is the charge stored across the gate, C is the gate capacitance and V is the gate voltage. While reduction in T
ox
increases the speed of the transistor, increased leakage due to tunneling through the gate insulator, results in increased power consumption.
FIG. 1
is a cross-sectional view of an FET illustrating tunneling current when the device is off. In
FIG. 1
, FET
100
includes a source
105
and a drain
110
formed in a silicon substrate
115
. Formed between source
105
and drain
110
is a channel region
120
. Formed over channel region
120
is a very thin gate dielectric
125
. Formed on top of gate dielectric
125
is gate electrode
130
. If FET
100
is an NFET, when a small (V
GATE
−V
SOURCE
<V
THESHOLD
) positive potential is applied to gate electrode
130
with respect to the source(device off), a small leakage current IGS flows between the gate electrode and the source
105
and a small leakage current IGD flows between the gate electrode and the drain
110
. If FET
100
is a PFET, when a negative potential is applied to gate electrode
130
with respect to its source (device off), a small leakage current IGS flows between the gate electrode and the source
105
and a small leakage current IGD flows between the gate electrode and the drain
110
. Both IGS and IGD are due to quantum mechanical tunneling of electrons through gate dielectric
125
.
FIG. 2
is a cross-sectional view of an FET illustrating tunneling current when the device is on. In
FIG. 2
, a voltage (positive for an NFET, negative for a PFET) has been applied to gate electrode
130
creating inversion layer
135
in channel region
120
. Inversion layer
135
electrically connects source
105
to drain
110
. In addition to the leakage currents IGS and IGD, a third leakage current IGC, flows from gate electrode
130
through gate dielectric
125
to inversion layer
135
and to substrate
115
. IGC is due to quantum mechanical tunneling of electrons from gate
130
through gate dielectric
125
. IGC is typically about 5X to 10X greater than IGS+IGD.
FIG. 3
is a plot of gate tunneling current vs. gate voltage as a function of gate dielectric thickness (SiO2.) For a 1.5 nm thick SiO2 gate and a gate voltage of 1.2 volts, the tunneling current through the gate dielectric is about 10 A/cm2. For a 1.0 nm thick SiO2 gate and a gate voltage of 1.2 volts, the tunneling current through the gate dielectric is about 1000 A/cm2. Clearly, a SiO2 gate-dielectric scaling limit exists. Therefore, for a typical CMOS circuit fabricated with very thin SiO2 gate dielectrics, nearly half the transistors, either the NFETs or the PFETs will exhibit a tunneling current during standby.
Circumventions to the scaling limit problem to date have been concentrated in the area of device physics employing non-conventional designs or materials. A circuit design that substantially mitigates the effect of tunneling leakage would extend the application of scaling for possibly one or two more conventional device generations.
BRIEF SUMMARY OF THE INVENTION
A first aspect of the present invention is a static CMOS circuit having an input and an output, comprising: a pass gate switch fabricated from thick oxide devices coupled between the input and a fast CMOS circuit fabricated from thin oxide devices, the fast CMOS circuit coupled to the output; and a slow CMOS circuit fabricated from thick oxide devices coupled between the input and the output.
A second aspect of the present invention is a static CMOS circuit having an input and an output, comprising: a pass gate switch fabricated from thick oxide devices coupled between the input and a fast CMOS circuit fabricated from thin oxide devices, the fast PCMOS circuit coupled to the output; a slow CMOS circuit fabricated from thick oxide devices coupled between the input and the output and a node; and a delay element coupled between the node and the output.
A third aspect of the present invention is an inverter having an input and an output, comprising: a pass gate switch fabricated from thick oxide devices coupled between the input and a fast inverter fabricated from thin oxide devices, the fast inverter coupled to the output; and a slow inverter fabricated from thick oxide devices coupled between the input and the output.
A fourth aspect of the present invention is an inverter having an input and an output, comprising: a pass gate switch fabricated from thick oxide devices coupled between the input and a fast inverter fabricated from thin oxide devices, the fast inverter coupled to the output; a slow inverter fabricated from thick oxide devices coupled between the input and the output and a node; and a delay element coupled between the node and the output.
A fifth aspect of the present invention is a NAND gate having a first and a second input and an output, comprising: a first pass gate switch fabricated from thick oxide devices coupled between the first input and a first input of a fast NAND gate fabricated from thin oxide devices, the fast NAND gate coupled to the output; a second pass gate switch fabricated from thick oxide devices coupled between the second input and a second input of the fast NAND gate; a slow NAND gate fabricated from thick oxide devices coupled between the first and the second inputs and the output.
A sixth aspect of the present invention is a static CMOS circuit having an input and an output, comprising: a fast CMOS circuit fabricated from thin oxide devices, the fast CMOS circuit having at least one input device, the fast CMOS circuit coupled to the output; a pass gate switch fabricated from thick oxide devices, the pass gate switch having one gate device coupled to each input device of the CMOS circuit, the pass gate switch coupled to the input; a slow CMOS circuit fabricated from thick oxide devices, coupled between the input and a node; and a delay element coupled between the node and the output.
A seventh aspect of the present invention is a static CMOS circuit having an input and an output, comprising: a fast CMOS circuit fabricated from thin oxide devices, the fast CMOS circuit having at least one input device, the fast CMOS circuit coupled to the output; a pass gate switch fabricated from thick oxide devices, the pass gate switch having one gate device coupled to each input device of the CMOS circuit, the pass gate switch coupled to the input; and a slow CMOS circuit fabricated from thick oxide devices, coupled between the input and the output.
An eighth aspect of the present invention is a static CMOS circuit having an input and an output, comprising: a fast CMOS circuit fabricated from thin oxide devices, the fast CMOS circuit having at l

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