Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-29
2003-07-15
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06594809
ABSTRACT:
TECHNICAL FIELD
The present invention broadly relates to the design, layout and fabrication of integrated circuits on a semiconductor chip, and deals more particularly with the insertion of antenna diodes in the integrated circuit in order to correct for antenna rule violations.
BACKGROUND OF THE INVENTION
Recent rapid advances in integrated circuit (IC) technology have created a number of challenges in the design, layout and fabrication of IC's at the chip level. The availability of sub 0.25 micron silicon technologies has permitted the fabrication of millions of logic gates on a single chip. Functions that were previously implemented across multiple chips are now being integrated onto a single chip. Circuit characteristics such as resistance and coupling capacitance, previously second order defects, are now first order defects in the environment of sub-quarter micron silicon technologies. At the same time, the increasingly competitive environment forces manufacturers to bring their chips to market in a shorter time interval. Often, the initial design, layout and mask fabrication can be very time consuming, even using electronic design automation (EDA) software. Even though the design process is highly automated, it is common to make manual changes to the final layout in order to achieve engineering change orders, foundry re-targeting and yield enhancement.
The design and layout of IC's consists of a number of steps that are performed in a pre-determined order. A general floor plan is first drawn up in which standard cells, taken from a library of cells, are laid out on the chip real estate. Each of these standard cells includes an electronic module or component. After the placement of the standard cells is determined, a routing step is performed in which electrical conductors are laid out or “routed” on the chip in order to interconnect the electronic modules with each other and with peripheral contact pads that are used to connect the IC with external circuitry. More specifically, during circuit layout synthesis, routing typically involves the connection of N-Type and P-Type transistors and signal input/output ports using electrical connections and applicable layers according to the electrical connectivity of the circuit being laid out. The applicable layers for interconnection usually include poly-silicon, diffusion and metal. Routing has a profound effect on the quality of the final compacted cell layout. Bad routing can lead to increased layout errors, poor electrical performance, and low yields.
Following the placement and routing, a series of design rule checks are performed to determine whether any of a number of known design rules have been violated by the final placement and routing. One of these design rules involves so-called “antenna rule violations”. Antenna rule violations are related to a phenomena in which certain of the routed conductors act as antennas that attract and store an electrical charge that is developed during the manufacturing process, typically during plasma etching. Plasma etching is a technique widely used in the fabrication of integrated circuits, wherein reactive ions are generated in an ion discharge and accelerated by an electrical field. These ions collide with the wafer surface carrying the semiconductor device being fabricated. The glow discharge used in plasma etching typically results in electrically charging some regions over the wafer surface. This charging can occur in a conductive layer region, for example at the poly-silicon gate formed over the surface of the wafer. A conductor line connected to the gate can act as antenna to store a charge during the etching process, thereby amplifying the charging effect. The static charge stored in the conductors connected to the input gates of transistors can ultimately discharge to the gate inputs, thereby destroying the transistor as well as the IC during the fabrication process. In order to avoid possible damage to the input gates caused by electrostatic discharge due to the antenna effect, protective diodes are sometimes installed at the input gates of transistors. These diodes are referred to as “antenna diodes” since they provide a discharge path to ground for the charges stored in the offending conductors.
In order to “insert” antenna diodes in a circuit to correct an antenna rule violation, antenna diodes were defined in so-called standard cells forming part of a library of cells used by the IC designer to aid in speeding up the design and layout process. However, because antenna diodes were previously laid out along with the other standard cells, it was necessary to provide ample “real estate” on a chip to accommodate a sufficient number of antenna diodes so that when it came time to correct antenna rule violations, the designer was assured that an antenna diode would be in close proximity to the conductor giving rise to the violation.
In addition to the effective waste of space on the IC chip resulting from the provision of a more than necessary number of antenna diodes, the large number of antenna diodes present on the chip gave rise to leakage currents. Leakage currents occur as a result of the fact that although not physically connected to the conductors, the diodes themselves were connected to ground and were placed in close proximity to the conductors. Although the leakage current through these diodes was small, because of the large number of diodes present on a chip, the total amount of leakage was sufficient to adversely effect circuit timing performance.
It would therefore be desirable to provide antenna diode insertion that reduces the overall amount of chip area required to correct antenna rule violations, while also reducing the amount of leakage current resulting from the presence of antenna diodes. The present invention is directed towards satisfying this need.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a method is provided for forming an integrated circuit on a chip, comprising the steps of laying out a plurality of electrical modules on the chip, wherein each of the modules is defined by a standard cell; establishing routing of conductors on a chip connecting the modules; laying out a plurality of filler cells on a chip; identifying antenna rule violations; and, correcting the antenna rule violations by selectively connecting the diode circuits with adjacent ones of conductors violating the antenna rules. The filler cells containing the antenna diodes are positioned in gaps lying between the standard cells. Each antenna diode circuit comprises a pair of diodes that are connected together in a circuit at the same time the antenna diode circuit is connected with a proximal conductor.
According to another aspect of the invention, an integrated circuit on a chip is provided, comprising a plurality of electrical modules defined in standard layout cells, wherein the standard cells are spaced apart to form gaps therebetween; a plurality of conductors on the chip forming electrical connections with the modules; a plurality of filler cells disposed within the gaps, certain of the filler cells containing an antenna diode circuit for discharging residual current present in an adjacent one of the conductors; and a plurality of electrically conductive links each connecting one of the conductors with one of the antenna diode circuits. Because the antenna diodes are formed in filler cells that ordinarily remain blank, the total area on the chip required for antenna diodes is substantially reduced. Since the diode in each diode circuit remains unconnected until the time of insertion, and the total number of antenna diodes is less than that previously required, the total amount of leakage current is reduced.
REFERENCES:
patent: 5901065 (1999-05-01), Guruswamy et al.
patent: 5966517 (1999-10-01), Cronin et al.
patent: 5984510 (1999-11-01), Guruswamy et al.
patent: 6308308 (2001-10-01), Cronin et al.
patent: 6389584 (2002-05-01), Kitahara
Hsiao Jun-Jyeh
Huang Wen-Hsiang
Su Hsiao-Pin
Wang Shao-Yu
Dinh Paul
Taiwan Semiconductor Manufacturing Co. Ltd.
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