Low leakage and data retention circuitry

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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C326S038000

Reexamination Certificate

active

07348804

ABSTRACT:
An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

REFERENCES:
patent: 5023480 (1991-06-01), Gieseke et al.
patent: 5274601 (1993-12-01), Kawahara et al.
patent: 5486774 (1996-01-01), Douseki et al.
patent: 5528173 (1996-06-01), Merritt et al.
patent: 5952865 (1999-09-01), Rigazio
patent: 5963054 (1999-10-01), Cochran et al.
patent: 5973552 (1999-10-01), Allan
patent: 6043698 (2000-03-01), Hill
patent: 6046627 (2000-04-01), Itoh et al.
patent: 6208171 (2001-03-01), Kumagai et al.
patent: 6246265 (2001-06-01), Ogawa
patent: 6288591 (2001-09-01), Riccio
patent: 6307233 (2001-10-01), Awaka et al.
patent: 6329874 (2001-12-01), Ye et al.
patent: 6384639 (2002-05-01), Chen et al.
patent: 6414534 (2002-07-01), Wang et al.
patent: 6437623 (2002-08-01), Hsu et al.
patent: 6437627 (2002-08-01), Tran et al.
patent: 6522171 (2003-02-01), Hanson et al.
patent: 6552601 (2003-04-01), Burr
patent: 6598148 (2003-07-01), Moore et al.
patent: 6621306 (2003-09-01), Ooishi et al.
patent: 6624687 (2003-09-01), Burr
patent: 6631502 (2003-10-01), Buffet et al.
patent: 6838901 (2005-01-01), Sakata et al.
patent: 6864718 (2005-03-01), Yu
patent: 6998895 (2006-02-01), Uvieghara
patent: 2004/0039954 (2004-02-01), White et al.
patent: 2004/0268278 (2004-12-01), Hoberman et al.
patent: 2006/0006929 (2006-01-01), Caplan et al.
Gupta, R., et al., “Low Power Wireless Networked System Design,” HotChips, Aug. 18, 2002, Stanford, CA.
Tsai, Y-F et al., “Implications of Technology Scaling on Leakage Reduction Techniques,” DAC 2003, Jun. 2-6, 2003, ACM, Anaheim, CA, USA.
Li L. et al., “Managing Leakage Energy in Cache Hierarchies,” Journal of Instruction-Level Parallelism, 2003, pp. 1-24, vol. 5.
Hu, J.S. et al., “Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch,” Proc. of IEEECS Annual Symposium on VLSI (ISVLSI 2003), Feb. 20-21, 2003, Tampa, Fl.
Zhang, W. et al., “Compiler Support for Reducing Leakage Energy Consumption,” Proceedings of the 6th Design Automation and Test in Europe Conference (DATE-03), Mar. 2003, Munich, Germany.
Degalahal, V. et al., “Analyzing Soft Errors in Leakage Optimized SRAM Design,” Proceedings of 16th International Conference on VLSI Design, Jan. 2003, New Delhi, India.
Li, L. et al., “Leakage Energy Management in Cache Hierarchies,” 11th International Conference on Parallel Architectures and Compilation Techniques (PACT'02), Sep. 2002.
Duarte, D. et al., “Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes,” Proceedings of the 20th International Conference on Computer Design (ICCD), Sep. 16-18, 2002, Freiberg, Germany.
Duarte, D. et al., “Impact of Technology Scaling and Packaging on Dynamic Voltage Scaling Techniques,” Proceedings of the 15th Annual IEEE International ASIC/SOC Conference, Sep. 25-28, 2002, Rochester, NY.
Kim, S et al. “Predictive Precharging for Bitline Leakage Energy Reduction,” Proceedings of 15th Annual IEEE International ASIC/SOC Conference, Sep. 25-28, 2002, Rochester, NY.
Ramanarayanan, R. et al. “Characterizing Dynamic and Leakage Power Behavior in Flip Flops,” Proceedings of the 15th Annual IEEE International ASIC/SOC Conference, Sep. 2002.
Chen, G. et al. “Adaptive Garbage Collection for Battery-Operated Environments,” Proceedings of USENIX JVM02 Symposium, Aug. 2002.
Chen, G. et al. “Energy Savings Through Compression in Embedded JavaEnvironments,” Proceedings of the CODES'02, Jun. 2002.
Delaluz, V. et al. “Hardware and Software Techniques for Controlling DRAM Power Modes,” IEEE Transaction on Computers, Nov. 2001, vol. 50.
Delaluz, V. et al. “Scheduler-Based DRAM Energy Management,” DAC 2002, Jun. 10-14, 2002, New Orleans, LA, USA, ACM.
Kim, S. et al. “Partitioned Instruction Cache Architecture for Energy Efficiency” ACM Transactions on Computational Logic, Jul. 2002, pp. 1-23, vol. V, No. N.
De La Luz, V. et al. “Automatic Data Migration for Reducting Energy Consumption in Multi-Bank Memory Systems,” DAC 2002, Jun. 10-14, 2002, New Orleans, LA, USA.
Duarte, D. et al. “Impact of Technology Scaling in the Clock System Power,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Apr. 25-26, 2002, Pittsburgh, PA.
Duarte, D. et al. “A Complete Phase-Locked Loop Power Consumption Model,” Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), IEEE.
Duarte, D. et al. “Evaluating Run-Time Techniques for Leakage Power Reduction,” Proceedings of the 15th International Conference on VLSI Design (VLSID'02) 2002, IEEE.
Zhang, W. “Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction,” Proceedings of the 34th Annual International Symposium on Microarchitecture (MICRO'01), Dec. 2001.
Kim, S. et al. “Energy Efficient Instruction Cache Using Page-Based Placement,” Proceedings of International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'01, Nov. 1-17, 2001, Atlanta, GA, USA.
Hezavei, J. et al. “Input Sensitive High-Level Power Analysis,” Proceedings of the 2001 IEEE Workshop on Signal Processing Systems (SiPS), Sep. 2001, pp. 149-156.
Kim, S. et al. “Power-aware Partitioned Cache Architectures,” Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design, 2001, ILSPED'01, Aug. 6-7, 2001, Huntington Beach, CA.
Delaluz, V. “DRAM Energy Management Using Software and Hardware Directed Power Mode Control,” Proceedings of the 7th International Symposium on High Performance Computer Architecture, Jan. 20-24, 2001, Monterrey, Mexico.
De Micheli, G. et al. “System-Level Power Optimization: Techniques and Tools,” Date 2000.
Manne, S. et al. “Cool Chips Tutorial,” 32nd Annual International Symposium on Microarchitecture, Nov. 15, 1999, Haifa, Israel.
Filseth, E. “Tally Power into Cost of ‘Free’ Silicon,” EETimes, Jan. 11, 1999, located at: http://www.eetimes.com/story/speakout/OEG19990111S028.
Frenkil, J. “A Multi-Level Approach to Low-Power IC Design,” IEEE Spectrum, Feb. 1998, Vo. 35, No. 2.
“Managing Power in Ultra Deep Submicron ASIC/IC Design,” May 2002, Synopsys, Inc.
Pangrle, B. “Low Power Design: A Holistic Approach in an Era of New Semiconductor Technologies,” San Diego Telecom Council Semiconductor SIG, Nov. 14, 2002.
Rabaey, J. “Design Aids for Low Power: Part II Architecture and System Levels,” 1997.
Grunwald, D. et al. “Kool Chips Workshop,” MICRO33, Dec. 10, 2000, Monterey, CA.
Flynn, J. et al., “Power Management in Complex SoC Design,” Synopsys, Apr. 2004, located at http://www.synopsys.com/sps.
Roy, K. et al., “Leakage Current Mechanisms and Leakage Reduction techniques in Deep-Submicrometer CMOS Circuits,” Proceedings of the IEEE, February 200, pp. 305-327, vol. 91, No. 2, IEEE.
Mutoh S., et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, No. 8, Aug. 1995, pp. 847-854.
Kawaguchi H., et al., “A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current,” IEEE Journal of Solid-State Circuits, vol. 35, No. 10, Oct. 2000, pp. 1498-1501.
Inukai T., et al., “Boosted

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