Low latency shared memory switch architecture

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Patent

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Details

370375, 370395, 395306, H04Q 1104

Patent

active

060318422

ABSTRACT:
A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

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